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Jain, Aman
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Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms
Singh K., Jain A., Mittal A., Yadav V., Singh A., Jain A., Gupta M. Integration, the VLSI Journal 60 25-38, 2018. Type: Article
This paper proposes a methodology for optimizing and evaluating chip designs by coupling the well-known logical effort (LE) theory with heuristic algorithms. Complementary metal–oxide–semiconductor (CMOS)-level optimization can dramati...
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Mar 1 2018
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