Search
A closed-form expression for estimating minimum operating voltage (V
DDmin
) of CMOS logic gates
Fuketa H., Iida S., Yasufuku T., Takamiya M., Nomura M., Shinohara H., Sakurai T. DAC 2011 (Proc. of the 48th Design Automation Conference, San Diego, CA, Jun 5-10, 2011)984-989,2011.Type:Proceedings
To:
Your Colleague's E-mail:
From:
Your E-mail:
Subject:
Reviews: A closed-form expression for estimating minimum operating voltage (V
DDmin
) of CMOS logic gates
Message Body:
Reproduction in whole or in part without permission is prohibited. Copyright 1999-2024 ThinkLoud
®
Terms of Use
|
Privacy Policy
