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	ACM Transactions on Architecture and Code Optimization (TACO) ACM Press         Options: Date Reviewed Title Author Publisher Published Date Descending Order Ascending Order     1-10 of 20 reviews Date Reviewed     Fast asymmetric thread synchronization Cleary J., Callanan O., Purcell M., Gregg D.  ACM Transactions on Architecture and Code Optimization (TACO) 9(4): 1-22, 2013. Type: Article The critical section problem involves code that accesses shared resources in a parallel computing environment. Managing such access is a difficult issue. Any solution to the critical section problem must consider both cooperation and competition... May 22 2013   A transactional memory with automatic performance tuning Wang Q., Kulkarni S., Cavazos J., Spear M.  ACM Transactions on Architecture and Code Optimization (TACO) 8(4): 1-23, 2012. Type: Article The concept of transactions in programming, introduced by Jim Gray in 1981, has been around for three decades. Only in the last few years has the programming language community warmed up to adopting transactions in general programming. The... Jul 12 2012   Using machine learning to improve automatic vectorization Stock K., Pouchet L., Sadayappan P.  ACM Transactions on Architecture and Code Optimization (TACO) 8(4): 1-23, 2012. Type: Article Getting good results from vectorizing code transformations requires searching an impractically large solution space. This paper describes machine learning techniques that organize the solution space so a compiler can use static program... Apr 25 2012   Towards update-conscious compilation for energy-efficient code dissemination in WSNs Li W., Zhang Y., Yang J., Zheng J.  ACM Transactions on Architecture and Code Optimization (TACO) 6(4): 1-33, 2009. Type: Article In this paper, Li et al. propose an update-conscious compilation (UCC) mechanism that reduces and minimizes the code size from the optimized intermediate representation (IR) stage to the binary code generation stage.... Jan 19 2011   Service level agreement for multithreaded processors Gabor R., Mendelson A., Weiss S.  ACM Transactions on Architecture and Code Optimization (TACO) 6(2): 1-33, 2009. Type: Article Multithreaded processors brought in the era where multiple processor threads not only share the memory storage space, as in symmetric multiprocessing (SMP) systems, but also share functional units such as pipelines, registers, and L1 caches. In... Sep 17 2009   Exploiting selective placement for low-cost memory protection Mehrara M., Austin T.  ACM Transactions on Architecture and Code Optimization (TACO) 5(3): 1-24, 2008. Type: Article This paper introduces a new, promising way of protecting embedded memory by exploring architecture alternatives--partial protection--and compiler optimizations--program profiling and selective placement of code and data in... Mar 5 2009   Reducing register pressure in SMT processors through L2-miss-driven early register release Sharkey J., Loew J., Ponomarev D.  ACM Transactions on Architecture and Code Optimization (TACO) 5(3): 1-28, 2008. Type: Article Superscalar processors and register renaming make it easy to simulate multiple processors on a single physical processor, improving the utilization of the computing units. When a memory reference to a location that is not in any... Feb 27 2009   Virtual machine showdown: stack versus registers Shi Y., Casey K., Ertl M., Gregg D.  ACM Transactions on Architecture and Code Optimization (TACO) 4(4): 1-36, 2008. Type: Article Programming language interpreters represent the executing program as an abstract machine. The major representation for Java is an abstract stack machine called Java bytecodes. The alternative representation is an abstract register machine. This... Aug 22 2008   Object co-location and memory reuse for Java programs Yu Z., Lau F., Wang C.  ACM Transactions on Architecture and Code Optimization (TACO) 4(4): 1-36, 2008. Type: Article Yu, Lau, and Wang have developed a memory management system called space-time efficient memory allocator (STEMA) for use in Java Virtual Machines. It is particularly effective for small memory devices. The paper defines the system and then... Aug 7 2008   Fairness enforcement in switch on event multithreading Gabor R., Weiss S., Mendelson A.  ACM Transactions on Architecture and Code Optimization (TACO) 4(3): 15-es, 2007. Type: Article Gabor et al. propose a heuristic to enforce fairness in switch on event (SOE) multithreading. In SOE, threads are switched on execution stalls such as cache misses. If left on their own, threads that rarely stall will consume all cycles, while... Apr 25 2008       Display 510152550100 per column
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