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Reviews in category "Register-Transfer-Level Implementation (B.5)": |
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FPGA technology mapping with encoded libraries and staged priority cuts
Kennings A., Vorwerk K., Kundu A., Pevzner V., Fox A. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4(4): 1-17, 2011. Type: Article |
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Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
Bombieri N., Fummi F., Pravadelli G. ACM Transactions on Design Automation of Electronic Systems 13(3): 1-22, 2008. Type: Article |
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Ajax bible
Holzner S., John Wiley & Sons, Inc., New York, NY, 2007. 695 pp. Type: Book (9780470102633) |
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Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Koch D., Haubelt C., Teich J. Field programmable gate arrays (Proceedings of the 2007 ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, Monterey, California, Feb 18-20, 2007) 188-196, 2007. Type: Proceedings |
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Implementing symmetric functions with hierarchical modules for stuck-at and path-delay fault testability
Rahaman H., Das D., Bhattacharya B. Journal of Electronic Testing: Theory and Applications 22(2): 125-142, 2006. Type: Article |
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