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  Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5)  
  Register-Transfer-Level Implementation (B.5) See Reviews  
General (13)
Design (14)
Design Aids (11)
Reliability And Testing (3)
Miscellaneous (2)
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Reviews in category "Register-Transfer-Level Implementation (B.5)":
Design optimization for security- and safety-critical distributed real-time applications
Jiang W., Pop P., Jiang K.  Microprocessors & Microsystems 52 401-415, 2017. Type: Article
Flash as cache extension for online transactional workloads
Kang W., Lee S., Moon B.  The VLDB Journal: The International Journal on Very Large Data Bases 25(5): 673-694, 2016. Type: Article
Performance prediction for Apache Spark platform
Wang K., Khan M.  HPCC, CSS & ICESS 2015 (Proceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf. on Embedded Software and Systems, Aug 24-26, 2015) 166-173, 2015. Type: Proceedings
Parallel programming model for the Epiphany many-core coprocessor using threaded MPI
Ross J., Richie D., Park S., Shires D.  Microprocessors & Microsystems 43(C): 95-103, 2016. Type: Article
Fast design exploration for performance, power and accuracy tradeoffs in FPGA-based accelerators
Ulusel O., Nepal K., Bahar R., Reda S.  ACM Transactions on Reconfigurable Technology and Systems 7(1): 1-22, 2014. Type: Article

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Reliability And Testing
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