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  Browse All Reviews > Hardware (B) > Logic Design (B.6) > Design Styles (B.6.1)
 
  Design Styles (B.6.1) See Reviews  
 
Subject Descriptors:
Cellular Arrays And Automata (20)
Combinational Logic (34)
Logic Arrays (38)
Memory Control And Access (4)
Memory Used As Logic (3)
Parallel Circuits (12)
Sequential Circuits (23)
 
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Reviews about "Design Styles (B.6.1)":
Date Reviewed
Optimization and quality estimation of circuit design via random region covering method
Bi Z., Zhou D., Wang S., Zeng X.  ACM Transactions on Design Automation of Electronic Systems 23(1): 1-25, 2017. Type: Article
Jan 26 2018
Towards ultra-efficient QCA reversible circuits
Chabi A., Roohi A., Khademolhosseini H., Sheikhfaal S., Angizi S., Navi K., DeMara R.  Microprocessors & Microsystems 49(C): 127-138, 2017. Type: Article
May 1 2017
Accelerating irregular computation in massive short reads mapping on FPGA co-processor
Tan G., Zhang C., Tang W., Zhang P., Sun N.  IEEE Transactions on Parallel and Distributed Systems 27(5): 1253-1264, 2016. Type: Article
Oct 4 2016
Reliability-aware design to suppress aging
Amrouch H., Khaleghi B., Gerstlauerz A., Henkel J.  DAC 2016 (Proceedings of the 53rd Annual Design Automation Conference, Austin, TX,  Jun 5-9, 2016) 1-6, 2016. Type: Proceedings
Jun 28 2016
Finite state machines in hardware: theory and design (with VHDL and SystemVerilog)
Pedroni V.,  The MIT Press, Cambridge, MA, 2013. 352 pp. Type: Book (978-0-262019-66-8)
Jul 10 2014
Using the minimum set of input combinations to minimize the area of local routing networks in logic clusters containing logically equivalent I/Os in FPGAs
Ye A.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(1): 95-107, 2010. Type: Article
Feb 8 2011
A low-power reconfigurable logic array based on double-gate transistors
Beckett P.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(2): 115-123, 2008. Type: Article
Aug 27 2008
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