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Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5) > Design (B.5.1) > Arithmetic And Logic Units (B.5.1...)
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1-7 of 7
Reviews about "Arithmetic And Logic Units (B.5.1...)":
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Synthesis of integer multipliers in sum of pseudoproducts form
Ciriani V., Luccio F., Pagli L. Integration, the VLSI Journal 36(3): 103-119, 2003. Type: Article
Ciriani, Luccio, and Pagli apply earlier work on sum of pseudoproducts (SPP) expressions of Boolean functions to the synthesis of integer multiplication circuits. A pseudoproduct is a generalization of the AND-products of Boolean varia...
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Mar 9 2004 |
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Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials
Zhang T., Parhi K. IEEE Transactions on Computers 50(7): 734-749, 2001. Type: Article
Finite field multiplication is a key operation in such areas as cryptography and error correction coding by block codes. The operation is far from trivial, since it involves a modulo operation with a primitive polynomial. This paper pr...
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Jun 13 2002 |
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Boosting Very-High Radix Division with Prescaling and Selection by Rounding
Montuschi P., Lang T. IEEE Transactions on Computers 50(1): 13-27, 2001. Type: Article
The authors discuss an algorithm for high radix division, and provide a hardware implementation....
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May 1 2001 |
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Hardware Implementation of Montgomery’s Modular Multiplication Algorithm
Eldridge S., Walter C. IEEE Transactions on Computers 42(6): 693-699, 1993. Type: Article
Hardware that quickly computes A × B mod M is described. The basic algorithm that this hardware uses for such computation is the one presented first by P. L. Montgomery [1] and further de...
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Oct 1 1994 |
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A Spanning Tree Carry Lookahead Adder
Lynch T., Earl E J. IEEE Transactions on Computers 41(8): 931-939, 1992. Type: Article
A classical problem in computer arithmetic, high-speed adder design, is revisited in this paper. The major novelty is in finding a good combination of two well-known techniques, carry lookahead and carry select. The combined adder cons...
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Oct 1 1993 |
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A General Proof for Overlapped Multiple-Bit Scanning Multiplications
Vassiliadis S., Schwarz E., Hanrahan D. IEEE Transactions on Computers 38(2): 172-183, 1989. Type: Article
This paper discusses multibit overlapped scanning techniques for the design of multipliers. The basis for this approach is the Booth recoding technique in which strings of 1s in the multiplier can be replaced by zeroes with a starting ...
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Jun 1 1990 |
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Square-rooting algorithms for high-speed digital circuits
Majerski S. IEEE Transactions on Computers 34(9): 724-733, 1985. Type: Article
The author’s research into algorithms for square root extraction of a number, or the sum of two numbers, will be of interest to hardware designers, microcode programmers, people working with array processors, and operating sy...
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Aug 1 1986 |
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