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	Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5) > Design Aids (B.5.2)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 13 Reviews about "Design Aids (B.5.2)": Date Reviewed   Design optimization for security- and safety-critical distributed real-time applications Jiang W., Pop P., Jiang K. Microprocessors & Microsystems 52 401-415, 2017.  Type: Article Security and design for real-time systems is becoming more relevant today than ever before. This is mostly due to the technology revolution moving toward automation and optimization, fueled by computer algorithms and software.... Dec 13 2017   Fast design exploration for performance, power and accuracy tradeoffs in FPGA-based accelerators Ulusel O., Nepal K., Bahar R., Reda S. ACM Transactions on Reconfigurable Technology and Systems 7(1): 1-22, 2014.  Type: Article Design space exploration is a critical development stage for hardware design. With the growing complexity of applications and the corresponding hardware we design to accelerate them, the task of exploring the wide variety of potential ... Jun 3 2014   FPGA technology mapping with encoded libraries and staged priority cuts Kennings A., Vorwerk K., Kundu A., Pevzner V., Fox A. ACM Transactions on Reconfigurable Technology and Systems 4(4): 1-17, 2011.  Type: Article Synthesis flow involves translating a given design into an unbound logic network, followed by a technology mapping phase that targets different technologies and implementation styles. In the case of field programmable gate arrays (FPGA... Jun 11 2012   Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow Bombieri N., Fummi F., Pravadelli G. ACM Transactions on Design Automation of Electronic Systems 13(3): 1-22, 2008.  Type: Article Transaction-based verification is a recent trend in hardware verification. The system is considered at higher levels of abstraction that model the data transfers and input/output (I/O) events between computational blocks, and functiona... Sep 18 2008   Writing testbenches: functional verification of HDL models (2nd ed.) Bergeron J., Kluwer Academic Publishers, Norwell, MA, 2003.  Type: Book (9781402074011) The best book ever published on the topic of verification was the first edition of this book [1]. Having used the first edition extensively, I must say how amazing it is that Bergeron, in his masterpiece second edition, did an even bet... Nov 16 2004   Symbolic RTL simulation Kölbl A., Kukula J., Damiano R.  Design automation (Proceedings of the 38th conference, Las Vegas, Nevada, United States, 47-52, 2001.  Type: Proceedings Symbolic simulation is a formal verification technique that adds thecapabilities of symbolic methods to conventional simulation methodologies. In symbolic simulation, for each input, a symbolic variable is introduced that represents al... Dec 1 2001   Electronic chips & systems design languages Mermet J. Kluwer Academic Publishers, Norwell, MA, 2001.  Type: Divisible Book The title of this book is somewhat ambiguous in English; a more accurate title would be Design languages for electronic chips and systems. The topics concern the issues surrounding the specification of complex systems in a forma... Sep 1 2001   An optimal clock period selection method based on slack minimization criteria Chang E., Gajski D., Narayan S. ACM Transactions on Design Automation of Electronic Systems 1(3): 352-370, 1996.  Type: Article In an automatic digital circuit synthesis system, the clock period is either specified by the designer or determined automatically by the synthesis system. The former situation occurs, for example, when the system under synthesis is pa... Sep 1 1997   A recursive technique for computing lower-bound performance of schedules Langevin M., Cerny E. ACM Transactions on Design Automation of Electronic Systems 1(4): 443-455, 1996.  Type: Article A recursive technique for estimating lower-bound performance of data path schedules is presented. The technique gives an improved complete lower bound in many cases where the Rim and Jain estimator was employed. In the introduction, th... Jul 1 1997   Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications Rim M., Jain R. IEEE Transactions on Parallel and Distributed Systems 7(4): 399-410, 1996.  Type: Article Rim and Jain present their paper in four sections: “Introduction,” “Valid Transformations,” “Examples,” and “Conclusion.” The introduction provides a lengt... Mar 1 1997       Display 510152550100 per page
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