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Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5) > Design Aids (B.5.2) > Hardware Description Languages (B.5.2...)
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Reviews about "Hardware Description Languages (B.5.2...)":
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Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
Bombieri N., Fummi F., Pravadelli G. ACM Transactions on Design Automation of Electronic Systems 13(3): 1-22, 2008. Type: Article
Transaction-based verification is a recent trend in hardware verification. The system is considered at higher levels of abstraction that model the data transfers and input/output (I/O) events between computational blocks, and functiona...
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Sep 18 2008 |
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Writing testbenches: functional verification of HDL models (2nd ed.)
Bergeron J., Kluwer Academic Publishers, Norwell, MA, 2003. Type: Book (9781402074011)
The best book ever published on the topic of verification was the first edition of this book [1]. Having used the first edition extensively, I must say how amazing it is that Bergeron, in his masterpiece second edition, did an even bet...
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Nov 16 2004 |
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Electronic chips & systems design languages
Mermet J. Kluwer Academic Publishers, Norwell, MA, 2001. Type: Divisible Book
The title of this book is somewhat ambiguous in English; a more accurate title would be Design languages for electronic chips and systems. The topics concern the issues surrounding the specification of complex systems in a forma...
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Sep 1 2001 |
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