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  Browse All Reviews > Hardware (B) > Logic Design (B.6) > Design Styles (B.6.1) > Combinational Logic (B.6.1...)  
 
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  1-7 of 7 Reviews about "Combinational Logic (B.6.1...)": Date Reviewed
  Using the minimum set of input combinations to minimize the area of local routing networks in logic clusters containing logically equivalent I/Os in FPGAs
Ye A. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(1): 95-107, 2010.  Type: Article

This is a very good academic paper, but it contains little of practical value to most design teams. It shows that the area of local routing networks that connect cluster inputs to individual lookup table (LUT) inputs can be significant...

Feb 8 2011
  Exact combinational logic synthesis and non-standard circuit design
Tarau P., Luderman B.  Computing frontiers (Proceedings of the 2008 Conference on Computing Frontiers, Ischia, Italy, May 5-7, 2008) 179-188, 2008.  Type: Proceedings

It is a common belief among engineers that symmetric operations are better for combinational logic synthesis. The authors here suggest that asymmetrical operators {<, =>} have better expressiveness, based on experimental ...

Jun 26 2008
  Combinational logic synthesis for LUT based field programmable gate arrays
Cong J., Ding Y. ACM Transactions on Design Automation of Electronic Systems 1(2): 145-204, 1996.  Type: Article

Research related to the design of logic circuits, both combinational and sequential, has been very productive. The variety of integrated chips (ICs) available to realize combinational functions is fairly large and ranges from basic gat...

Feb 1 1997
  An Efficient Implementation of Boolean Functions as Self-Timed Circuits
David I., Ginosar R., Yoeli M. IEEE Transactions on Computers 41(1): 2-11, 1992.  Type: Article

The design of self-timed logic (STL) is an important part of VLSI design. STL circuits assure that events will occur in a sequence, but no event needs to occur at any particular time. This paper addresses two issues of STL: the efficie...

Jun 1 1993
  Latch-to-Latch Timing Rules
Champernowne A., Bushard L., Rusterholz J., Schomburg J. IEEE Transactions on Computers 39(6): 798-808, 1990.  Type: Article

The design of a digital system involves combinatorial circuits, latches, and clock circuits that require a careful timing analysis. Because of the delays introduced by the modules, it is necessary to ensure that the signals arrive at p...

Jul 1 1991
  Computational Complexity of Controllability/Observability Problems for Combinational Circuits
Fujiwara H. IEEE Transactions on Computers 39(6): 762-767, 1990.  Type: Article

The most important problem this paper deals with seems to be the “observability problem.” Let C be a combinational circuit, and let A and B be particular input and output lines, respectively. Is there an assignment ...

May 1 1991
  Graph-based algorithms for Boolean function manipulation
Bryant R. IEEE Transactions on Computers 35(9): 677-691, 1986.  Type: Article

This paper develops new data structures to represent Boolean functions. These functions are described by means of directed, acyclic graphs, in a manner that resembles the binary decision diagrams introduced by Lee [1] and Akers [2]. In...

Jul 1 1987
 
 
 
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