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  Browse All Reviews > Hardware (B) > Logic Design (B.6) > Miscellaneous (B.6.m)  
 
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  1-7 of 7 Reviews about "Miscellaneous (B.6.m)": Date Reviewed
  Energy efficiency: a new concern for application software developers
Pinto G., Castor F.  Communications of the ACM 60(12): 68-75, 2017. Type: Article

This article focuses on energy savings for distributed computer systems, particularly using autonomous devices such as smartphones. According to the authors, this problem “is hindered by a lack of knowledge and a lack of tools.” Yet in...

Apr 6 2018
  RT level timing modeling for aging prediction
Koppaetzky N., Metzdorf M., Eilers R., Helms D., Nebel W.  DATE 2016 (Proceedings of the 2016 Conference on Design, Automation & Test in Europe, Dresden, Germany,  Mar 14-18, 2016) 297-300, 2016. Type: Proceedings

Transistor aging has grown as a critical reliability issue that shortens the lifetime of electronic devices and slows down the circuits inside these devices. During the past decade, researchers have proposed various techniques to deal with aging-r...

Sep 9 2016
  Novel state minimization and state assignment in finite state machine design for low-power portable devices
Shiue W.  Integration, the VLSI Journal 38(4): 549-570, 2005. Type: Article

The goal of the paper is to develop synthesis techniques for the next-state logic in finite state machines (FSMs) to optimize power, area, and delay. While technically sound, numerous grammatical, typographical, and figure errors cloud the present...

Feb 17 2006
  Discrete neural computation
Siu K. (ed), Roychowdhury V., Kailath T.,  Prentice-Hall, Inc., Upper Saddle River, NJ, 1995.Type: Book (9780133007084)

In the past decade, there has been growing interest in neural networks and their applications in such disciplines as neurobiology, computer science, engineering, mathematics, and physics. This book brings together recent developments in discrete n...

Jan 1 1996
  Latch-to-Latch Timing Rules
Champernowne A., Bushard L., Rusterholz J., Schomburg J.  IEEE Transactions on Computers 39(6): 798-808, 1990. Type: Article

The design of a digital system involves combinatorial circuits, latches, and clock circuits that require a careful timing analysis. Because of the delays introduced by the modules, it is necessary to ensure that the signals arrive at proper times ...

Jul 1 1991
  Designing multibus priority resolver by means of a field programmable logic sequencer
Constantinescu C.  Microprocessing and Microprogramming 13(5): 325-330, 1984. Type: Article

This paper presents a design of a bus priority resolver for Multibus using a Programmable Logic Array (PLA). It contains all the necessary technical information required to duplicate the design. The material is clear and well presented. However, t...

Nov 1 1985
  Reverse engineering the brain
Stevens J.  BYTE 10(4): 287-299, 1985. Type: Article

Artificial Intelligence has two sides: mimicking human intelligence by performing similar tasks, and modeling the natural structures and functions. This article appears under a banner of “Artificial Intelligence,” probably because it d...

Oct 1 1985
 
 
 
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