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	Browse All Reviews > Hardware (B) > Integrated Circuits (B.7) > Types And Design Styles (B.7.1) > Algorithms Implemented In Hardware (B.7.1...)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 23 Reviews about "Algorithms Implemented In Hardware (B.7.1...)": Date Reviewed   FPGA-based hardware acceleration of lithographic aerial image simulation Cong J., Zou Y. ACM Transactions on Reconfigurable Technology and Systems 2(3): 1-29, 2009.  Type: Article In high-performance reconfigurable computing (HPRC), a reconfigurable device is used to accelerate some parts of a computing-intensive application. HPRC is an emerging field, and its importance can be seen in the number of companies th... Mar 16 2010   FPGA-based hardware acceleration for Boolean satisfiability Gulati K., Paul S., Khatri S., Patil S., Jas A. ACM Transactions on Design Automation of Electronic Systems 14(2): 1-11, 2009.  Type: Article The Boolean satisfiability (SAT) problem is the most important nondeterministic polynomial time (NP) complete problem, since it is key to defining all of the other NP-complete problems. Since other NP-complete problems can be converted... Aug 18 2009   FPGA acceleration of RankBoost in Web search engines Xu N., Cai X., Gao R., Zhang L., Hsu F. ACM Transactions on Reconfigurable Technology and Systems 1(4): 1-19, 2009.  Type: Article Web search engines have changed our lives. The possibility of introducing a search term and having millions of results in less than a second puts an amazing amount of knowledge in our hands. One of the main problems in facing this incr... Jun 1 2009   Concurrent error detection in Reed-Solomon encoders and decoders Cardarilli G., Pontarelli S., Re M., Salsano A. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(7): 842-846, 2007.  Type: Article Reed-Solomon (RS) error-correcting codes are able to detect and correct errors in transmission and storage systems and are used in a wide variety of commercial applications, such as DVD, worldwide interoperability for microwave access ... Jan 24 2008   An algorithm for adaptive mean filtering and its hardware implementation Gasteratos I., Gasteratos A., Andreadis I. Journal of VLSI Signal Processing Systems 44(1-2): 63-78, 2006.  Type: Article A hardware-oriented filtering algorithm for noise reduction using a mean filter is proposed in this paper. The authors elaborate the effect of classical and contemporary filters, and show that those filters reduce noise at the cost of ... Feb 22 2007    Area and power reduction of embedded DSP systems using instruction compression and re-configurable encoding Chandar S., Mehendale M., Govindarajan R. Journal of VLSI Signal Processing Systems 44(3): 245-267, 2006.  Type: Article When designing consumer electronics products, energy use and chip memory size are key issues. Since more than 15 percent of the energy consumed when using such devices comes from program memory accesses--that is, when central ... Jan 24 2007   The fast evaluation strategy for evolvable hardware Salami M., Hendtlass T. Genetic Programming and Evolvable Machines 6(2): 139-162, 2005.  Type: Article If an evolutionary algorithm is implemented in hardware, one expects a substantial speed up. However, for problems where the computation of the fitness function is a large part of the execution, this may not be the case. This paper des... Oct 26 2006   A hardware/software co-design of MP3 audio decoder Tsai T., Yang Y., Liu C. Journal of VLSI Signal Processing Systems 41(1): 111-127, 2005.  Type: Article Moving Picture Experts Group (MPEG) decoding is a complex process: a decoder must read the MPEG data stream, decode its pieces, and then perform the proper transforms to generate an audio signal as output. The demand for low-cost, low-... Jun 28 2006   Countersniper system for urban warfare Lédeczi Á., Nádas A., Völgyesi P., Balogh G., Kusy B., Sallai J., Pap G., Dóra S., Molnár K., Maróti M., Simon G. ACM Transactions on Sensor Networks 1(2): 153-177, 2005.  Type: Article This paper is a compressive and concise disclosure, relating to a real-world, real-time application for a wireless sensor network. Specifically, this is a detailed case study of the design, integration, and testing of acoustic sensors ... Mar 8 2006   A 2 Gb/s balanced AES crypto-chip implementation Guürkaynak F., Burg A., Felber N., Fichtner W., Gasser D., Hug F., Kaeslin H.  Great Lakes Symposium on VLSI (Proceedings of the 14th ACM Great Lakes Symposium on VLSI, Boston, MA, USA, Apr 26-28, 2004) 39-44, 2004.  Type: Proceedings This paper describes the design of a two-gigabit-per-second (Gb/s) cryptography chip that implements the American Encryption Standard (AES) algorithm, while supporting all standard operating modes and key lengths. The chip̵... Apr 15 2005       Display 510152550100 per page
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