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	Browse All Reviews > Hardware (B) > Integrated Circuits (B.7) > Design Aids (B.7.2)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 193 Reviews about "Design Aids (B.7.2)": Date Reviewed   Accuracy-configurable adder for approximate arithmetic designs Kahng A., Kang S.  DAC 2012 (Proceedings of the 49th Annual Design Automation Conference, San Francisco, CA,  Jun 3-7, 2012) 820-825, 2012. Type: Proceedings This paper introduces a new accuracy-configurable approximate (ACA) adder that can be configured during runtime. In the past, various approximate adders have been proposed for error-tolerant applications. Compared to conventional adders, these... Jan 30 2013   Behavior-level observability analysis for operation gating in low-power behavioral synthesis Cong J., Liu B., Majumdar R., Zhang Z.  ACM Transactions on Design Automation of Electronic Systems 16(1): 1-29, 2010. Type: Article As the authors demonstrate in this paper, observability analysis at the behavioral level, before operations are scheduled, can lead to significant reductions in power consumption. This is done by gating clocks on the output registers of the gated ... Mar 2 2011   Increasing the locality of iterative methods and its application to the simulation of semiconductor devices Pichel J., Heras D., Cabaleiro J., García-Loureiro A., Rivera F.  International Journal of High Performance Computing Applications 24(2): 136-153, 2010. Type: Article Many scientific programming applications are based on computational models involving nonlinear partial differential equations. These equations are solved via discretization approaches such as the finite element method. The resulting equations... Jul 28 2010   FPGA-based acceleration of CHARMM-potential minimization Sukhwani B., Herbordt M.  HPRCTA 2009 (Proceedings of the 3rd International Workshop on High-Performance Reconfigurable Computing Technology and Applications, Portland, Oregon,  Nov 15, 2009) 1-10, 2009. Type: Proceedings Molecular dynamic simulation is a high-performance computing (HPC) application that is computationally intensive, with longer runtimes. Molecular docking determines the “least energy pose” between two interacting proteins. During... Apr 1 2010   A real-time program trace compressor utilizing double move-to-front method Uzelac V., Milenkovic A.  DAC 2009 (Proc. of the 46th Annual Design Automation Conference, San Francisco, California,  Jul 26-31, 2009) 738-743, 2009. Type: Proceedings The move-to-front (MTF) transform is a standard data compression technique that reduces the entropy of data streams. After a symbol has been processed, it is moved to the top of the history table, which ensures that frequently used symbols are... Jan 15 2010   A memetic approach to the automatic design of high-performance analog integrated circuits Liu B., Fernández F., Gielen G., Castro-López R., Roca E.  ACM Transactions on Design Automation of Electronic Systems 14(3): 1-24, 2009. Type: Article This interesting paper summarizes work for the incremental improvement of automatic analog design and optimization, by leveraging capabilities of multiple existing leading algorithms. Although the proposed algorithm is an aggregate of a few... Sep 9 2009   MaizeRouter: engineering an effective global router Moffitt M.  ASP-DAC 2008 (Proceedings of the 2008 Asia and South Pacific Design Automation Conference, Seoul, Korea,  Jan 21-24, 2008) 226-231, 2008. Type: Proceedings Routing is an essential step in the process of modern very large-scale integration (VLSI) physical design. Without an effective and efficient router, it is difficult to implement the physical layout of an integrated circuit that may contain... Apr 17 2009   FPGA prototyping by VHDL examples: Xilinx Spartan-3 version Chu P.,  Wiley-Interscience, 2008. 468 pp. Type: Book Owing to the advancement of semiconductor fabrication technology and electronic design automation (EDA) tools, field-programmable gate array (FPGA) and very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) ... Feb 18 2009   A low-power reconfigurable logic array based on double-gate transistors Beckett P.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(2): 115-123, 2008. Type: Article A reconfigurable architecture, based on double-gate (DG) transistor circuits, that could be suitable for implementing low-power reconfigurable logic arrays, targeting future nanoscale technologies, is discussed in this paper. The operation of DG... Aug 27 2008   Temperature-insensitive synthesis using multi-VT libraries Calimera A., Macii E., Poncino M., Bahar R.  VLSI (Proceedings of the 18th ACM Great Lakes Symposium on VLSI, Orlando, Florida,  May 4-6, 2008) 5-10, 2008. Type: Proceedings Technology advancement in nanometer very large-scale integration (VLSI) design demands smarter synthesis algorithms to automatically generate circuits with high speed and low power. Multiple-threshold voltage (Vt) devices are being employed more... Aug 1 2008       Display 510152550100 per page
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