Search for Topics All Reviews
	Browse All Reviews > Hardware (B) > Integrated Circuits (B.7) > Reliability And Testing (B.7.3)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 18 Reviews about "Reliability And Testing (B.7.3)": Date Reviewed   DFM evaluation using IC diagnosis data Blanton R., Wang F., Xue C., Nag P., Xue Y., Li X. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36(3): 463-474, 2017.  Type: Article During the processes of designing and manufacturing integrated circuits, the yield, which is calculated as the percentage of manufactured integrated circuits that pass all of the tests and function properly, is one of the major concern... Apr 27 2018   Parallel Signature Analysis Design with Bounds on Aliasing Saxena N., McCluskey E. IEEE Transactions on Computers 46(4): 425-438, 1997.  Type: Article As chip densities increase, conventional methods of testing become more difficult. One way around this problem is to use the extra circuitry made available by including self-test logic on the chip. Typically, the self-test circuitry in... Nov 1 1997   AVPGEN--a test generator for architecture verification Chandra A., Iyengar V., Jameson D., Jawalekar R., Nair I., Rosen B., Mullen M., Yoon J., Armoni R., Geist D., Wolfsthal Y. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(2): 188-200, 1995.  Type: Article AVPGEN is a system that assists in the creation of tests for the verification of a processor architecture. It consists of a database of processor features; a language, SIGL, in which test templates can be specified; and a supervisor th... Jan 1 1996   Fault covering problems in reconfigurable VLSI systems Libeskind-Hadas R., Hasan N., Cong J., McKinley P., Liu C., Kluwer Academic Publishers, Norwell, MA, 1992.  Type: Book (9780792392316) Recent research results on reconfiguration problems in VLSI and wafer-scale integration (WSI) systems are reported. The goal of this research was to develop efficient algorithms for the fault covering approach. In the first chapter, a ... Sep 1 1993   Silicon compilation of hierarchical control sections with unified BIST testability Nicolaidis M., Torki K., Jerraya A., Courtois B. (ed) Microprocessors & Microsystems 15(5): 257-269, 1991.  Type: Article The fault testing of integrated circuits has been a prolific research field. One recently popular method is called BIST (built-in self-test). This paper describes an automatic synthesis tool that builds up the control section of a micr... Jun 1 1992   Built-In Testing of Integrated Circuit Wafers Rangarajan S., Fussell D., Malek M. IEEE Transactions on Computers 39(2): 195-205, 1990.  Type: Article Assume that a wafer contains an array of identical integrated circuits, that a test can be applied to all of these in parallel, and that the test results for each IC can be compared. In the usual case a test is applied and the results ... Mar 1 1991   Selecting test methodologies for PLAs and random logic modules in VLSI circuits--an expert systems approach Bhawmik S., Narang V., Chaudhuri P. Integration, the VLSI Journal 7(3): 267-281, 1989.  Type: Article Design for testability (DFT) involves methods of designing circuits and systems to make the creation of tests for manufacturing defects easier. A wide range of DFT techniques exist. Each method involves certain costs in such terms as c... Aug 1 1990   Gentest: An Automatic Test-Generation System for Sequential Circuits Cheng W., Chakraborty T. Computer 22(4): 43-49, 1989.  Type: Article Gentest is a new system for the automatic generation of test sequences for sequential circuits. After a rather general survey of typical problems in test pattern generation, this paper outlines the Gentest architecture with an emphasis... Jul 1 1990   Whistle: A Workbench for Test Development of Library-Based Designs Renous R., Silberman G., Spillinger I. Computer 22(4): 27-41, 1989.  Type: Article The authors use the difference fault model (DFM) to design a PL/I-based environment for library-based circuit design and verification on functional blocks. They also carry out fault simulation, fault injection, and syntax-directed desi... Jan 1 1990   Design for testability of a 32-bit TRON microprocessor Nozuyama Y., Nishimura A., Iwamura J. Microprocessors & Microsystems 13(1): 17-27, 1989.  Type: Article Many techniques exist for improving the testability of integrated circuits, and many papers describe them. A paper that describes how some of these techniques are combined in a real integrated circuit, however, is not so common. This p... Oct 1 1989       Display 510152550100 per page
	Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud® Terms of Use | Privacy Policy