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  Browse All Reviews > Computer Systems Organization (C) > Processor Architectures (C.1) > Single Data Stream Architectures (C.1.1)  
 
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  1-10 of 30 Reviews about "Single Data Stream Architectures (C.1.1)": Date Reviewed
  Computational memory: a stepping stone to non-von Neumann computing?
Abu Sebastian. YouTube, 01:20:34, published on Mar 8, 2018, stanfordonline, https://www.youtube.com/watch?v=_2Wiql4QSLQ. Type: Video

The topic of this video presentation is computational memory (CM), a seemingly fascinating new paradigm in computing. The presenter’s approach to the topic is captivating; when you start the video, you just want to proceed fo...

Sep 27 2018
  Reducing register pressure in SMT processors through L2-miss-driven early register release
Sharkey J., Loew J., Ponomarev D. ACM Transactions on Architecture and Code Optimization 5(3): 1-28, 2008.  Type: Article

Superscalar processors and register renaming make it easy to simulate multiple processors on a single physical processor, improving the utilization of the computing units. When a memory reference to a location that is no...

Feb 27 2009
  Lazy instruction scheduling: keeping performance, reducing power
Mahjur A., Taghizadeh M., Jahangir A.  Low power electronics and design (Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design, Bangalore, India, Aug 11-13, 2008) 375-380, 2008.  Type: Proceedings

The problem of “useless instruction execution” is addressed in this paper. An instruction is useless if the result is never used. With reasonable compilers, this problem can only take place when conditional branches...

Nov 20 2008
  Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors
Homayoun H., Pasricha S., Makhzan M., Veidenbaum A. ACM SIGPLAN Notices 43(7): 71-78, 2008.  Type: Article

Homayoun et al. contend that increasing the size of processor resources is not an effective way to improve performance, due to constraints on achievable clock frequency during operation. In fact, while increasing the size of processor ...

Sep 15 2008
  An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors
Mutlu O., Kim H., Armstrong D., Patt Y. IEEE Transactions on Computers 54(12): 1556-1571, 2005.  Type: Article

The paper quantifies the importance of including wrong-path memory references in the simulation environment of a superscalar processor at various degrees of speculation. The authors did an excellent job in the background section, with ...

Jul 4 2006
  An FPGA-based VLIW processor with custom hardware execution
Jones A., Hoare R., Kusic D., Fazekas J., Foster J.  Field-programmable gate arrays (Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-programmable Gate Arrays, Monterey, California, Feb 20-22, 2005) 107-117, 2005.  Type: Proceedings

This is a very exciting piece of research in the general area of configurable, extensible processors and the software/hardware interface. The authors propose a hybrid architecture, consisting of a parameterized very long instruction wo...

May 23 2006
  Design of a multimedia processor based on metrics computation
Amor N., Le Moullec Y., Diguet J., Philippe J., Abid M. Advances in Engineering Software 36(7): 448-458, 2005.  Type: Article

A novel approach for the creation of a multimedia processor is presented in this paper. Three steps to customize a general-purpose processor (GPP) based on the detailed analysis of a target application are described, and these steps ar...

Jan 5 2006
  Fast branch misprediction recovery in out-of-order superscalar processors
Zhou P., Önder S., Carr S.  Supercomputing (Proceedings of the 19th Annual International Conference on Supercomputing, Cambridge, Massachusetts, Jun 20-22, 2005) 41-50, 2005.  Type: Proceedings

This paper proposes a mechanism, eager misprediction recovery (EMR), for recovering the processor state after branch misprediction in modern out-of-order architectures. The idea of this mechanism is to restart the instruction fetching ...

Dec 13 2005
  Instruction packing: reducing power and delay of the dynamic scheduling logic
Sharkey J., Ponomarev D., Ghose K., Ergin O.  Low power electronics and design (Proceedings of the 2005 International Symposium on Low Power Electronics and Design, San Diego, CA, Aug 8-10, 2005) 30-35, 2005.  Type: Proceedings

A new technique, instruction packing, is proposed in this paper, for use in the microarchitectures of superscalar processors. Traditionally, instructions are scheduled dynamically, using instruction queues (IQs). In instruction packing...

Oct 21 2005
  A cost-effective design for MPEG-2 audio decoder with embedded RISC core
Tsai T., Wu R., Chen L. Journal of VLSI Signal Processing Systems 29(3): 255-265, 2001.  Type: Article

The reproduction of MPEG audio files is becoming a hot topic in both the scientific and entertainment arenas, motivating a lot of research in the area with the goal of achieving high performance with contained power consumption. Since ...

Apr 21 2003
 
 
 
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