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Browse All Reviews > Computer Systems Organization (C) > Processor Architectures (C.1) > Single Data Stream Architectures (C.1.1) > Pipeline Processors (C.1.1...)
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1-3 of 3
Reviews about "Pipeline Processors (C.1.1...)":
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A study of scalar compilation techniques for pipelined supercomputers
Weiss S., Smith J. ACM Transactions on Mathematical Software 16(3): 223-245, 1990. Type: Article
This research paper reports on performance improvements for pipelined scientific computers provided by two scalar compilation techniques: loop unrolling and software pipelining. Architectural features to support the techniques are also...
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Jun 1 1991 |
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Dynamic Instruction Scheduling and the Astronautics ZS-1
Smith J. Computer 22(7): 21-35, 1989. Type: Article
Smith is a member of the project team for the Astronautics ZS-1. The ZS-1 is a high-speed computer system for scientific applications. It uses two instruction pipelines, one for fixed-point and memory addressing operations, the other f...
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Oct 1 1990 |
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Measurement and evaluation of the MIPS architecture and processor
Gross T., Hennessy J., Przybylski S., Rowen C. ACM Transactions on Computer Systems 6(3): 229-257, 1988. Type: Article
This paper presents the results of a large number of measurements on the performance of MIPS, a 32-bit reduced instruction set computer (RISC) architecture implemented at Stanford University between 1981 and 1984 as a single-chip micro...
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Apr 1 1989 |
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