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	Browse All Reviews > Hardware (B) > Performance And Reliability (B.8)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 57 Reviews about "Performance And Reliability (B.8)": Date Reviewed   Tolerating transient illegal turn faults in NoCs Huang L., Zhang X., Ebrahimi M., Li G. Microprocessors & Microsystems 43(C): 104-115, 2016.  Type: Article Faults in on-chip level networks are very common. There have been multiple approaches to detect and correct faults in different levels, such as the error-detecting code (EDC) and error-correcting code (ECC) used in the data packet, cyc... Jul 29 2016   Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources Giannopoulou G., Stoimenov N., Huang P., Thiele L., Dupont de Dinechin B. Real-Time Systems 52(4): 399-449, 2016.  Type: Article Giannopoulou and colleagues describe their approach for the scheduling of mixed-criticality applications on many-core systems. The paper initially provides an overview of solutions for the scheduling and mapping of this kind of applica... Jul 5 2016   Methodology to verify, debug and evaluate performances of NoC based interconnects Oury P., Heaton N., Penman S.  NoCArc 2015 (Proceedings of the 8th International Workshop on Network on Chip Architectures, Waikiki, HI, Dec 5, 2015) 39-42, 2015.  Type: Proceedings The authors of this paper introduce some verification issues regarding systems on chip (SoC) structures and transfer protocols, and further introduce some of the means available to achieve network on chip (NoC) design correctness and a... Feb 22 2016   Execution trace-driven energy-reliability optimization for multimedia MPSoCs Das A., Singh A., Kumar A. ACM Transactions on Reconfigurable Technology and Systems 8(3): 1-19, 2015.  Type: Article Dynamic task scheduling and fault tolerance in multiprocessor systems-on-chip (MPSoCs) are explored in this paper. The paper describes a heterogeneous MPSoC system with a special fault-free node called RTM to manage the other processin... Aug 19 2015   Characterization, monitoring and evaluation of operational performance trends on server processor hardware Sithole E., McClean S., Scotney B., Parr G., Moore A., Bustard D., Dawson S., Bustard D.  ICPE 2011 (Proceeding of the 2nd Joint WOSP/SIPEW International Conference on Performance Engineering, Karlsruhe, Germany, Mar 14-16, 2011) 391-402, 2011.  Type: Proceedings With the increase in data-intensive applications, enterprise information technology (IT) companies are focusing on the performance of processor hardware to determine the optimal central processing unit (CPU) and memory selection.... Dec 20 2011   Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure Kim K., Wong A., Lipson H. Genetic Programming and Evolvable Machines 11(1): 35-59, 2010.  Type: Article When talking about fault tolerance, we seek to put in place mechanisms that would keep a system running with minimal degradation, despite the malfunctioning of a component. Typically, in the case of failure, redundant components jump i... Aug 19 2010   How green is green? Want R. IEEE Pervasive Computing 8(1): 2-4, 2009.  Type: Article Using pervasive computing, Want attempts to relate a variety of concerns about energy conservation and carbon dioxide (CO2) emissions.... Jul 7 2010   GRID codes: strip-based erasure codes with high fault tolerance for storage systems Li M., Shu J., Zheng W. ACM Transactions on Storage 4(4): 1-22, 2009.  Type: Article As the authors correctly suggest in the introduction, no code is perfect and selecting code for an application always involves tradeoffs. Although GRID codes--“a new family of erasure codes with high fault tolerance&... May 26 2010   Selective replication: a lightweight technique for soft errors Vera X., Abella J., Carretero J., González A. ACM Transactions on Computer Systems 27(4): 1-30, 2009.  Type: Article By selectively replicating only those instructions that have the highest probability of failing due to soft errors--caused by particle strikes, noise, electromagnetic interference, or electrostatic discharge--Vera et ... Mar 11 2010   Automatic test generation for combinational threshold logic networks Gupta P., Zhang R., Jha N. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(8): 1035-1045, 2008.  Type: Article Two nanoscale devices that implement threshold logic are resonant tunneling diodes (RTDs) and quantum cellular automata (QCA). A threshold logic gate (TLG) computes the sign of the weighted sum of its inputs, compared with a threshold.... Jun 12 2009       Display 510152550100 per page
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