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	Browse All Reviews > Computer Systems Organization (C) > Processor Architectures (C.1) > Single Data Stream Architectures (C.1.1) > RISC/CISC, VLIW Architectures (C.1.1...)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 10 Reviews about "RISC/CISC, VLIW Architectures (C.1.1...)": Date Reviewed   Lazy instruction scheduling: keeping performance, reducing power Mahjur A., Taghizadeh M., Jahangir A.  Low power electronics and design (Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design, Bangalore, India,  Aug 11-13, 2008) 375-380, 2008. Type: Proceedings The problem of “useless instruction execution” is addressed in this paper. An instruction is useless if the result is never used. With reasonable compilers, this problem can only take place when conditional branches occur between the... Nov 20 2008   ASIP instruction encoding for energy and area reduction Morgan P., Taylor R.  Design automation (Proceedings of the 44th Annual Conference on Design Automation, San Diego, California,  Jun 4-8, 2007) 797-800, 2007. Type: Proceedings Application-specific very long instruction word (VLIW) instruction processors are developed to reduce area and energy consumption. This interesting paper proposes to convert some of the most frequent opcodes to short opcodes, using additional... Oct 10 2007   An FPGA-based VLIW processor with custom hardware execution Jones A., Hoare R., Kusic D., Fazekas J., Foster J.  Field-programmable gate arrays (Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-programmable Gate Arrays, Monterey, California,  Feb 20-22, 2005) 107-117, 2005. Type: Proceedings This is a very exciting piece of research in the general area of configurable, extensible processors and the software/hardware interface. The authors propose a hybrid architecture, consisting of a parameterized very long instruction word (VLIW)... May 23 2006   LZW-based code compression for VLIW embedded systems Lin C., Xie Y., Wolf W.  Design, automation and test in Europe (Proceedings of the Conference on Design, Automation and Test in Europe, Paris, France,  Feb 16-20, 2004) 76-81, 2004. Type: Proceedings This is a relevant piece of work in the domain of dynamic code compression and decompression in deeply embedded central processing units. The authors identify the code between two branch/jump targets as a potentially good candidate for... Mar 3 2006   Design of a multimedia processor based on metrics computation Amor N., Le Moullec Y., Diguet J., Philippe J., Abid M.  Advances in Engineering Software 36(7): 448-458, 2005. Type: Article A novel approach for the creation of a multimedia processor is presented in this paper. Three steps to customize a general-purpose processor (GPP) based on the detailed analysis of a target application are described, and these steps are... Jan 5 2006   Guide to assembly language programming in Linux Dandamudi S.,  Springer-Verlag New York, Inc., Secaucus, NJ, 2005. 552 pp. Type: Book Many books on assembly language programming for Intel machines appear on the bookshelves of any library, a situation easily explained by the success of the IA-32 architecture and its availability. Assembly language programming deals with... Dec 22 2005   Guide to RISC processors: for programmers and engineers Dandamudi S.,  Springer-Verlag New York, Inc., Secaucus, NJ, 2005. 387 pp. Type: Book An elementary introduction to reduced instruction set computing (RISC) processors, with an overall emphasis on the machine-level language and not on functional chip design, is presented in this book. It is split into three sections: a brief... Sep 22 2005   Time optimal software pipelining of loops with control flows Yun H., Kim J., Moon S.  International Journal of Parallel Programming 31(5): 339-391, 2003. Type: Article This paper is in the area of compiler optimizations for processors, such as very long instruction word (VLIW) and super scalar, processors which exploit instruction-level parallelism. A well-known technique is software pipelining of loops in the... Nov 26 2004   A cost-effective design for MPEG-2 audio decoder with embedded RISC core Tsai T., Wu R., Chen L.  Journal of VLSI Signal Processing Systems 29(3): 255-265, 2001. Type: Article The reproduction of MPEG audio files is becoming a hot topic in both the scientific and entertainment arenas, motivating a lot of research in the area with the goal of achieving high performance with contained power consumption. Since the... Apr 21 2003   Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures López D., Llosa J., Valero M., Ayguadé E.  IEEE Transactions on Computers 50(10): 1033-1051, 2001. Type: Article The authors of this paper have done an excellent job in illustrating the various aspects of looping constructs that affect instruction-level parallelism (ILP) in the course of program execution.... Dec 16 2002       Display 510152550100 per page
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