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	Browse All Reviews > Hardware (B) > Memory Structures (B.3)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 110 Reviews about "Memory Structures (B.3)": Date Reviewed   A study of pointer-chasing performance on shared-memory processor-FPGA systems Weisz G., Melber J., Wang Y., Fleming K., Nurvitadhi E., Hoe J.  FPGA 2016 (Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, Feb 21-23, 2016) 264-273, 2016.  Type: Proceedings Several vendors including Intel and IBM have announced devices that closely integrate processors and field programmable gate arrays (FPGAs) using low-latency shared memory interfaces. This paper examines the potential of such devices f... Jun 7 2017   A SISO register circuit tailored for input data with low transition probability Napoli E., Castellano G., De Caro D., Esposito D., Petra N., Strollo A. IEEE Transactions on Computers 66(1): 45-51, 2017.  Type: Article There are occasions when a delay of several clock cycles is required for a serial data stream. If the “density” of transitions is low, meaning the probability of transitions with respect to the clock is small, and t... May 31 2017   Evaluating the combined effect of memory capacity and concurrency for many-core chip design Liu Y., Sun X. ACM Transactions on Modeling and Performance Evaluation of Computing Systems 2(2): 1-25, 2017.  Type: Article With the increase in data-intensive computation, effective design space exploration (DSE) of on-chip multiprocessors (CMPs) has become crucial to improve the performance and accuracy of the same. Existing models primarily consider eith... May 11 2017   Optimizing data placement on GPU memory: a portable approach Chen G., Shen X., Wu B., Li D. IEEE Transactions on Computers 66(3): 473-487, 2017.  Type: Article We say that a computational artifact is “portable” if it can be implemented on a variety of targets. In this paper, the portable artifact is a strategy for the placement of data on a graphics processing unit (GPU). ... Apr 17 2017   Dynamic core allocation and packet scheduling in multicore network processors Iqbal M., Holt J., Ryoo J., de Veciana G., John L. IEEE Transactions on Computers 65(12): 3646-3660, 2016.  Type: Article The invention of the multicore processor was a great achievement with significant influences on the throughput, performance, and speed of computing. It has been the origin of two major investigation streams: how to exploit its untether... Mar 31 2017   Flash as cache extension for online transactional workloads Kang W., Lee S., Moon B. The VLDB Journal: The International Journal on Very Large Data Bases 25(5): 673-694, 2016.  Type: Article Very large databases always need fast and reliable operations. Existing SQL engine and object-relational mapping (ORM) implementations take advantage of efficient in-memory caching mechanisms, which can really make the difference in te... Dec 20 2016   Improving write performance by controlling target resistance distributions in MLC PRAM Kim Y., Yoo S., Lee S. ACM Transactions on Design Automation of Electronic Systems 21(2): 1-27, 2016.  Type: Article Memory technology is important to everyone who wants his computer to be faster. Dynamic random-access memory (DRAM) has been used as the main memory technology for decades, but it has some overhead related to its cost and power consump... Apr 19 2016   Memristor based computation-in-memory architecture for data-intensive applications Hamdioui S., Xie L., Nguyen H., Taouil M., Bertels K., Corporaal H., Jiao H., Catthoor F., Wouters D., Eike L., van Lunteren J.  DATE 2015 (Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, Grenoble, France, Mar 9-13, 2015) 1718-1725, 2015.  Type: Proceedings Big data problems have exposed the limitations of traditional computer architecture based on von Neumann’s computational paradigm, where data and programs are stored away from the computational element, and need to be transpo... Sep 23 2015   GPU concurrency: weak behaviours and programming assumptions Alglave J., Batty M., Donaldson A., Gopalakrishnan G., Ketema J., Poetzl D., Sorensen T., Wickerson J.  ASPLOS 2015 (Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems, Istanbul, Turkey, Mar 14-18, 2015) 577-591, 2015.  Type: Proceedings A memory consistency model (MCM) is a specification that describes the value(s) that a memory location should hold based on the causal history of operations that may or may not be associated with that location. The MCM specification is... Jul 16 2015   More than Moore technologies for next generation computer design Topaloglu R., Springer Publishing Company, Incorporated, New York, NY, 2015. 218 pp.  Type: Book (978-1-493921-62-1) This year, we are celebrating the 50-year anniversary of Moore’s law. On April 19, 1965, Gordon Moore published a four-page paper titled “Cramming more components onto integrated circuits.” This paper made... Jul 2 2015       Display 510152550100 per page
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