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	Browse All Reviews > Hardware (B) > Memory Structures (B.3) > Design Styles (B.3.2)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 76 Reviews about "Design Styles (B.3.2)": Date Reviewed   Evaluating the combined effect of memory capacity and concurrency for many-core chip design Liu Y., Sun X. ACM Transactions on Modeling and Performance Evaluation of Computing Systems 2(2): 1-25, 2017.  Type: Article With the increase in data-intensive computation, effective design space exploration (DSE) of on-chip multiprocessors (CMPs) has become crucial to improve the performance and accuracy of the same. Existing models primarily consider eith... May 11 2017   Cache vulnerability mitigation using an adaptive cache coherence protocol Maghsoudloo M., Zarandi H. The Journal of Supercomputing 68(3): 1048-1067, 2014.  Type: Article Soft errors in on-chip cache hierarchies are studied in this paper, and solutions to the problem are proposed. Soft errors are the result of events such as cosmic ray strikes that flip bits held in on-die transistors. Due to shrinking ... Jul 28 2014   Towards virtual shared memory for non-cache-coherent multicore systems Ramesh B., Ribbens C., Varadarajan S.  IPDPSW 2013 (Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops,May 20-24, 2013) 1186-1193, 2013.  Type: Proceedings Samhita, an implementation of distributed shared memory (DSM), is discussed in this paper. DSM enables a programmer to view a collection of compute nodes, each with its own physical memory, as a single shared memory, greatly simplifyin... Dec 4 2013   Hybrid nonvolatile disk cache for energy-efficient and high-performance systems Shi L., Li J., Jason Xue C., Zhou X. ACM Transactions on Design Automation of Electronic Systems 18(1): 1-23, 2012.  Type: Article This paper presents the construction of a hybrid cache for magnetic disks built from a combination of phase change memory (PCM) and more traditional flash memory. Unlike traditional flash memory, PCM is byte addressable, enables in-pla... Jun 14 2013   An efficient cache strategy for improving images’ quality Cheng H., Wu T., Lee W.  ICIMCS 2009 (Proceedings of the 1st International Conference on Internet Multimedia Computing and Service, Kunming, Yunnan, China, Nov 23-25, 2009) 49-52, 2009.  Type: Proceedings Distributing videos to Internet users in real time will always be a challenging problem. A client-server-based architecture faces the predicament of server capability when handling a flux of requests. Therefore, peer-to-peer (P2P) syst... May 21 2010   Efficient memory management for hardware accelerated Java Virtual Machines Bertels P., Heirman W., D’Hollander E., Stroobandt D. ACM Transactions on Design Automation of Electronic Systems 14(4): 1-18, 2009.  Type: Article Bertels et al. study the problem of memory allocation in an environment that includes both a general processor and an attached hardware accelerator. In the model studied, memory is shared between the two processors, with all memory acc... Nov 11 2009    Utilizing shared data in chip multiprocessors with the Nahalal architecture Guz Z., Keidar I., Kolodny A., Weiser U.  SPAA 2008 (Proceedings of the 20th Annual Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, Jun 14-16, 2008) 1-10, 2008.  Type: Proceedings In a multicore processor chip, the L2 cache may be organized as one private L2 cache per core or a single shared L2 cache. The private cache approach requires smaller caches than a shared cache, and thus has faster cache access time th... Dec 23 2008   Heterogeneously tagged caches for low-power embedded systems with virtual memory support Zhou X., Petrov P. ACM Transactions on Design Automation of Electronic Systems 13(2): 1-24, 2008.  Type: Article Zhou and Petrov propose a cache architecture that aims to provide fast data access and low power consumption.... Dec 5 2008   Modeling and evaluating heterogeneous memory architectures by trace-driven simulation Wang W., Wang Q., Wei W., Liu D.  Memory access on future processors (Proceedings of the 2008 Workshop on Memory Access on Future Processors, Ischia, Italy, May 5-7, 2008) 369-376, 2008.  Type: Proceedings Much effort is devoted to improving the memory performance of processors, which have an obvious performance bottleneck in their memory systems.... Sep 11 2008   ASIP instruction encoding for energy and area reduction Morgan P., Taylor R.  Design automation (Proceedings of the 44th Annual Conference on Design Automation, San Diego, California, Jun 4-8, 2007) 797-800, 2007.  Type: Proceedings Application-specific very long instruction word (VLIW) instruction processors are developed to reduce area and energy consumption. This interesting paper proposes to convert some of the most frequent opcodes to short opcodes, using add... Oct 10 2007       Display 510152550100 per page
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