Search for Topics All Reviews
	Browse All Reviews > Hardware (B) > Memory Structures (B.3) > Design Styles (B.3.2) > Cache Memories (B.3.2...)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-10 of 35 Reviews about "Cache Memories (B.3.2...)": Date Reviewed   Cache vulnerability mitigation using an adaptive cache coherence protocol Maghsoudloo M., Zarandi H. The Journal of Supercomputing 68(3): 1048-1067, 2014.  Type: Article Soft errors in on-chip cache hierarchies are studied in this paper, and solutions to the problem are proposed. Soft errors are the result of events such as cosmic ray strikes that flip bits held in on-die transistors. Due to shrinking ... Jul 28 2014   An efficient cache strategy for improving images’ quality Cheng H., Wu T., Lee W.  ICIMCS 2009 (Proceedings of the 1st International Conference on Internet Multimedia Computing and Service, Kunming, Yunnan, China, Nov 23-25, 2009) 49-52, 2009.  Type: Proceedings Distributing videos to Internet users in real time will always be a challenging problem. A client-server-based architecture faces the predicament of server capability when handling a flux of requests. Therefore, peer-to-peer (P2P) syst... May 21 2010    Utilizing shared data in chip multiprocessors with the Nahalal architecture Guz Z., Keidar I., Kolodny A., Weiser U.  SPAA 2008 (Proceedings of the 20th Annual Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, Jun 14-16, 2008) 1-10, 2008.  Type: Proceedings In a multicore processor chip, the L2 cache may be organized as one private L2 cache per core or a single shared L2 cache. The private cache approach requires smaller caches than a shared cache, and thus has faster cache access time th... Dec 23 2008   Heterogeneously tagged caches for low-power embedded systems with virtual memory support Zhou X., Petrov P. ACM Transactions on Design Automation of Electronic Systems 13(2): 1-24, 2008.  Type: Article Zhou and Petrov propose a cache architecture that aims to provide fast data access and low power consumption.... Dec 5 2008   ASIP instruction encoding for energy and area reduction Morgan P., Taylor R.  Design automation (Proceedings of the 44th Annual Conference on Design Automation, San Diego, California, Jun 4-8, 2007) 797-800, 2007.  Type: Proceedings Application-specific very long instruction word (VLIW) instruction processors are developed to reduce area and energy consumption. This interesting paper proposes to convert some of the most frequent opcodes to short opcodes, using add... Oct 10 2007   Selective-splitting and cache-maintenance algorithms for associative-client caches Gao J., Quass D., Ng Y. Distributed and Parallel Databases 16(1): 5-43, 2004.  Type: Article Traditional caching mechanisms work by storing individual items (relational tuples, pages, or objects) in caches; thus, their contents can be exploited only if future requests address these items by their IDs (tuple-id, object-id, and ... Oct 18 2005   Low-Power High-Performance Reconfigurable Computing Cache Architectures Sangireddy R., Kim H., Somani A. IEEE Transactions on Computers 53(10): 1274-1290, 2004.  Type: Article This paper addresses the problems associated with large caches, and the fact that some workloads do not necessarily benefit from them. The authors propose reconfiguring part of the cache as a processing unit for multimedia applications... Jun 23 2005   Cache optimization for embedded processor cores: an analytical approach Ghosh A., Givargis T. ACM Transactions on Design Automation of Electronic Systems 9(4): 419-440, 2004.  Type: Article This paper presents the authors’ insights into how customized cache subsystems can improve the performance of applications employing embedded microprocessor cores.... Dec 17 2004   A self-tuning cache architecture for embedded systems Zhang C., Vahid F., Lysecky R. ACM Transactions on Embedded Computing Systems 3(2): 407-425, 2004.  Type: Article Tunable cache organization, particularly for embedded systems, is discussed in this paper. Its motivation is that 60 percent of the energy in embedded systems is spent in cache. To reduce such energy consumption--currently one... Aug 10 2004   Execution history guided instruction prefetching Zhang Y., Haga S., Barua R. The Journal of Supercomputing 27(2): 129-147, 2004.  Type: Article Zhang, Haga, and Barua propose a new hardware-based I-cache correlated prefetch algorithm called “execution guided history method.” Their main idea is to correlate cache misses to instructions executed in a delta-ti... Aug 6 2004       Display 510152550100 per page
	Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud® Terms of Use | Privacy Policy