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ComputingReviews.com
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A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates Fuketa H., Iida S., Yasufuku T., Takamiya M., Nomura M., Shinohara H., Sakurai T. DAC 2011 (Proc. of the 48th Design Automation Conference, San Diego, CA, Jun 5-10, 2011)984-989,2011.Type:Proceedings |
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