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	Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms Singh K., Jain A., Mittal A., Yadav V., Singh A., Jain A., Gupta M. Integration, the VLSI Journal60 25-38,2018.Type:Article     Published By: Elsevier Science Publishers B. V.       Use your personal or institutional subscription to read the fulltext of the article.               You can purchase an article without having a subscription.
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