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A triple modular redundancy technique providing multiple-bit error protection without using extra redundancy
van Gils W. IEEE Transactions on Computers35 (7):623-631,1986.Type:Article
Date Reviewed: Nov 1 1986

An analysis of the frequency and types of error encountered in semiconductor memory units indicates that for long-period accuracy, some form of checking is necessary. In this paper, a simple model is used to illustrate polling techniques and, in particular, the usual Triple Modular Redundancy (TMR) method. It is then pointed out that bitwise polling in conventional TMR systems does not always detect some types of component failure.

The author proposes a new system based upon redundancy coding, but not adding to the system complexity. A derivation, based upon Galois theory, is provided. This is a potentially valuable technique which will find application in new defense systems.

Reviewer:  A. D. Booth Review #: CR110945
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Redundant Design (B.3.4 ... )
 
 
Error-Checking (B.3.4 ... )
 
 
Error-Checking (B.7.3 ... )
 
 
Information Theory (H.1.1 ... )
 
 
Memory Design (B.5.1 ... )
 
 
Memory Technologies (B.7.1 ... )
 
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