The paper presents a method for solving the complex and yet insufficiently explored problem of fault tolerance in configurable multiprocessor systems. The complexity of this problem resides in the difficulty of securing various topologies that comply with the communication requirements of parallel algorithms. The proposed scheme attempts to minimize configurability degradation caused by processor failures. The key idea of this approach is to change the logical structure of the multiprocessor system so as to maintain a fault-free subsystem that provides the same configurability as the original system but with fewer processors. The authors focus on processor failures and their effects on system configurability. They do not discuss network component failures or the problem of detecting and locating the defective processors. The central idea behind the proposed scheme is to use two transformations to restore a linear address space in the presence of processor failures. The fault-tolerant mapping scheme is composed of three algorithms. The algorithms use the two transformations adaptively to handle three different types of faults: single fault, double fault, and triple or multiple fault.

Lin and Wu have written a practical paper. The proposed fault-tolerant mapping scheme is presented in a concise, clear manner and should be used when designing configurable multiprocessor systems.