Design for testability (DFT) involves methods of designing circuits and systems to make the creation of tests for manufacturing defects easier. A wide range of DFT techniques exist. Each method involves certain costs in such terms as circuit overhead, test creation time, and performance impact, and each is appropriate for a different set of designs.

This paper presents an expert system approach for selecting the appropriate DFT technique for a design. A motivation vector is defined for the evaluation measures appropriate for a system. For a PLA, the measures might be

• maximize fault coverage,

• minimize test application time,

• minimize logic overhead, and

• minimize additional I/O signals.

Using an expert system for this job is overkill. The search space for DFT techniques is not so large that the search could not be done manually given a collection of appropriate techniques. The process of defining a motivation vector is valuable, however, in that it forces a designer to quantify the tradeoffs that have to be made for testability. The authors give examples for PLA testability techniques, which are well understood, and random logic testability techniques, which are not. They demonstrate the general applicability of this process. The authors make the excellent observation that test specifications are for the entire chip, not just for a module such as a PLA. This explains why the motivation vector must consist of relative values. Unfortunately, their technique does not address the problem of avoiding local optimization at the expense of full system testability. Nonetheless, I recommend this paper to all those involved in testable design, since it contains suggestions that can be of immediate use.