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3D parity checking models for errors in RAM memories used in space on-board computers
Kuo N., Gough M. Microprocessors & Microsystems12 (7):599-605,1988.Type:Article
Date Reviewed: Jan 1 1992

The authors describe their research on three-dimensional parity schemes for fault-tolerant applications. The title is somewhat limiting in that the schemes are useful for other fault-tolerant applications as well.

The authors compare three schemes--the traditional two-dimensional parity checking system, and pseudo and real three-dimensional systems. The models are compared in terms of their ability to detect errors and the amount of additional overhead (memory chips) required. The paper explains the calculations used in the comparison, yet remains concise and easy to read.

Individuals wishing to investigate different types of parity checking schemes would find the paper useful. The explanations make it useful for an academic course in fault-tolerant computing.

Reviewer:  R. J. DeMattia Review #: CR115124
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Error-Checking (B.3.4 ... )
 
 
Formal Models (B.3.3 ... )
 
 
Design Styles (B.3.2 )
 
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