In VLSI design, macro-cell placement arranges rectangular blocks of arbitrary widths and heights on the chip. The goal is to minimize the chip size and to reduce the total wire length of the nets connecting different blocks. This paper proposes a divide-and-conquer with hierarchy placement (DCHP) method. The DCHP method is divided into two stages: finding a good arrangement to minimize the chip size, and then rearranging the blocks to minimize the wire length. Two other methods are described for comparison. The overlap placement (OP) method uses a penalty function to penalize the overlap of blocks. The slicing placement (SP) method uses a normalized polish expression to represent the placement. All three placement methods use a simulated annealing approach to search for the solution.

The experiments on the first three test cases show that OP is a clear winner in reducing the total wire length. They also show that DCHP reaches a local minimal solution in a short time, while a longer execution time is needed for OP and SP to achieve their best solutions. Further experiments on MCNC test cases are suggested for a conclusive comparison.