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Silicon compilation of hierarchical control sections with unified BIST testability
Nicolaidis M., Torki K., Jerraya A., Courtois B. (ed) Microprocessors & Microsystems15 (5):257-269,1991.Type:Article
Date Reviewed: Jun 1 1992

The fault testing of integrated circuits has been a prolific research field. One recently popular method is called BIST (built-in self-test). This paper describes an automatic synthesis tool that builds up the control section of a microprocessor from its behavioral description according to the universal BIST (UBIST) technique. The authors use an existing control section compiler, called SYCO.

The paper opens with a section on definitions and properties of self-testing circuits. The next section summarizes the UBIST technique. The UBIST control section is then discussed. Since this section contains PLAs (programmable logic arrays), the authors go on to describe self-checking of PLAs, with the help of Berger and double-rail code. This scheme is already available in the literature. The authors describe the adaptation of these schemes for their purpose. The following section describes new tools developed by the authors, namely, PROTECT to code the PLA module and two tools to determine test patterns and generate descriptions of different blocks. The final two sections discuss fault coverage and give conclusions. Three appendices deal with excitation of self-checking circuits, implementation of secure PLAs with CMOS logic, and testability of checkers.

The paper is well written, logically organized, and well illustrated. The technical matters contained in the paper are discussed thoroughly. The modifications done are particular to a specific compiler, however, and may not be useful for others. Nonetheless, the paper is certainly useful as a case study.

Reviewer:  Arun Ektare Review #: CR115955
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