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Transputer hardware and system design
Hinton J., Pinder A., Prentice-Hall, Inc., Upper Saddle River, NJ, 1993. Type: Book (9780139530012)
Date Reviewed: Feb 1 1995

Transputers are a family of microprocessors created by  INMOS,  now owned by SGI Thompson. Transputers are fast RISC processors that were especially designed to facilitate simple single-processor as well as multiprocessor designs. To achieve the first goal, transputers are highly integrated (computers on a chip); they include an external memory interface (SRAM and DRAM controller) and internal memory. Transputers can operate when connected solely to power and a clock signal, since four high-speed serial links can provide I/O. These links can also be used to connect multiple transputers, and the instruction set has built-in multitasking support. These two features simplify the design of multiprocessor systems.

This book is intended as a practical guide to transputer hardware design. The authors do not assume prior knowledge of the transputer architecture, but the reader should be familiar with more conventional microprocessor design.

The book gives a brief introduction to the transputer architecture, focusing on its novel features. For example, it has parallel programming support for processes and interprocess communication, which is based on the communicating sequential programming (CSP) model by Hoare. Chapter 2 briefly introduces the transputer’s instruction set.

Two different types of external memory interfaces are available, one that supports fast static RAM (two-cycle) and one that is programmable and is mainly intended for slower dynamic memory (three-cycle). Chapters 3 and 4 describe the two-cycle memory interface. This interface uses separate data and address buses. Therefore, it is only supported on the 16-bit transputers and on a special version (T801) of the 32-bit processors. Chapter 4 includes three design examples: a 62256 SRAM, a DAC (AD667), and an ADC (AD7572) interface.

The three-cycle memory interface described in chapter5 is intended for dynamic RAM (DRAM) systems and other complex memory-mapped I/O devices. The address and data buses are multiplexed to reduce the number of pins. The three-cycle external memory interface contains several programmable strobe signals that can be used to create chip select, output enable, or row/column address signals. Furthermore, the refresh is fully supported on chip. Therefore, all that is required to connect up to 2 MB of DRAM to a transputer are address latches to de-multiplex the data and address buses. Chapter 6 contains design examples for slow semirandom access memory (SRAM), DRAM, and combined DRAM/ROM systems.

Chapter 7 covers transputer interconnections. Although shared-memory systems are possible, the transputer model assumes that each processor contains only local resources (memory, disk drives, and so on) and all interconnections are done using the on-chip links. INMOS offers two link adaptor chips that allow users to connect transputers to other processors (C012 or C011 Mode 2) or to parallel ports (C011 Mode 1). Chapter 7 also introduces the C004 programmable interconnection chip, which allows flexible interprocessor connections. The chapter covers interfacing to an ADC using a link adaptor chip (C011) and includes some general information on how to connect a link adaptor to the PC ISA bus.

Since debugging and testing multiprocessor systems is inherently more complex than sequential computer systems, the authors dedicate chapter 8 to the debugging facilities of the transputer. Transputers provide a special signal that allows postmortem debugging, peek, and poke of transputer networks. Debugging transputer systems is only considered in the context of system testing, however. Readers interested in tracking bugs in application programs will be disappointed.

Chapter 9 describes the next generation of transputers, the T9000. This new transputer chip has been advertised for a year, but is not yet available, and the information in the book is preliminary. Therefore, the T9000 chapter does not include sufficient information for T9000 design. It is of more descriptive than practical design value.

The appendix contains some excerpts from the transputer data sheets, PAL design equations for some of the design examples, and some sample programs for system testing. The book also contains an adequate index and bibliography.

Much of the information presented in this book is available in more detail elsewhere, for example the transputer data sheets and the INMOS OCCAM 2 reference manual. This is particularly true for the introductory chapters covering the parallel processing model (processes, channels, and OCCAM) and the transputer architecture. The chapters covering the two-cycle and three-cycle memory interfaces are useful, however, since they cover different design possibilities and include some practical tips and pitfalls of transputer system design. Overall, the book can be recommended as a good starting point, but readers should not expect a complete design without additional information.

Reviewer:  Jacky Baltes Review #: CR117578
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Inmos Transputer (C.5.3 ... )
 
 
Microprocessors And Microcomputers (B.7.1 ... )
 
 
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Other reviews under "Inmos Transputer": Date
Transputer applications in robotics for dynamic modelling and path planning
Morris A. (ed), Zalzala A., Zomaya A. Microprocessors & Microsystems 12(7): 565-572, 1988. Type: Article
Jun 1 1992
Transputer technical notes
, Prentice-Hall, Inc., Upper Saddle River, NJ, 1989. Type: Book (9789780139291265)
May 1 1990

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