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AVPGEN--a test generator for architecture verification
Chandra A., Iyengar V., Jameson D., Jawalekar R., Nair I., Rosen B., Mullen M., Yoon J., Armoni R., Geist D., Wolfsthal Y. IEEE Transactions on Very Large Scale Integration (VLSI) Systems3 (2):188-200,1995.Type:Article
Date Reviewed: Jan 1 1996

AVPGEN is a system that assists in the creation of tests for the verification of a processor architecture. It consists of a database of processor features; a language, SIGL, in which test templates can be specified; and a supervisor that controls the test generation process. SIGL allows the use of symbolic values and constraints.

Though certainly not fully automatic, AVPGEN seems like an excellent advance in solving the problem of providing enough high-quality test cases to give some degree of confidence in the correctness of large computers. It has been used to help debug the IBM S/390 CPU. It is particularly useful in creating many tests for complex features of an architecture.

The paper is well written, using a simple but useful example to demonstrate the operation of AVPGEN.

Reviewer:  S. Davidson Review #: CR119413 (9601-0036)
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Test Generation (B.7.3 ... )
 
 
VLSI (Very Large Scale Integration) (B.7.1 ... )
 
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