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Testing and testable design of high-density random-access memories
Mazumder P. (ed), Chakraborty K., Kluwer Academic Publishers, Norwell, MA, 1996. Type: Book (9780792397823)
Date Reviewed: Nov 1 1997

. This is a compendium of state-of-the-art literature on diverse aspects of testing and testable design of random access memories (RAMs), intended for design engineers and manufacturers of RAMs. The authors consider over 180 research papers that are included in the bibliography and cited in the text.

The first chapter is a particularly good summary of the characteristics of modern memory. It introduces random access memory and describes the technical advances that have been achieved in this component over the last two decades. It defines the various types of memory cells, such as bipolar, charged coupled, magnetic bubbles, complementary metal on silicon (CMOS), and N-channel MOS (NMOS). The authors then contrast memory cell designs, distinguishing clearly between static and dynamic memory cells.

The authors note the importance of the circuit implementation of the memory. I like to think of memory as a functional unit that consists of memory cells, decoders, control, sense amplifiers, multiplex addressing, a timing change phase/restore generator, and delayed drivers. The authors examine the basic read/write mechanisms for this functional unit. They also present a brief history of memory processing and circuit technology.

Application-specific functional memory units are then addressed. The authors discuss the similarities and differences between specific RAM designs: pseudo-DRAM (dynamic RAM) that is  embedded  in integrated circuits, battery backup DRAM, high-speed DRAM, video DRAM, dual port memory, and content addressable memory. They examine techniques for improving memory performance to increase speed or reduce power. They also pay attention to high-density multi-megabyte memory.

The second chapter examines electrical testing, considering it in three phases: testing modules and their external connections during manufacture; testing them after manufacture to reject defective modules; and checking the memory while it is in use, in case faults develop. This chapter points out the importance of choosing a proper fault model. Once the modules come off the assembly line, we want to identify the ones that should be rejected. The first method uses characterization tests. These tests provide a test sequence that either results in a pass/fail decision or uses a statistically significant sample as a basis for rejecting an entire batch. The production test often subjects the module to normal or even excessive conditions during a period called the burn in. This should eliminate most of the unfit modules, with the expectation that the rest will continue to operate properly in normal use over their expected lifetimes.

The authors describe an example SRAM, the TMS4016, including its pin arrangement and operation. They then examine its parametric testing as an example of this testing method.

The remaining three chapters lucidly describe and discuss relevant aspects of random access memories. Chapter 3 is devoted to functional fault modeling and testing, divided into two areas: design-independent fault modeling and testing, and layout-dependent models.

The fourth chapter delves more deeply into RAM technology and layout-oriented testing. It examines parametric testing first. Then it examines fault models, tests, and other items, with an emphasis on cell design, processing technology, and layout.

The fifth chapter considers how to build self-testing into the system and, thus, to design for testability. It considers both traditional and modern approaches.

A final chapter presents conclusions. There are three appendices: a glossary, commercial RAM data, and some information about the current market for RAMs. The book concludes with a set of references and an index.

Reviewer:  Ivan Flores Review #: CR120905 (9711-0854)
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