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Parallel Signature Analysis Design with Bounds on Aliasing
Saxena N., McCluskey E. IEEE Transactions on Computers46 (4):425-438,1997.Type:Article
Date Reviewed: Nov 1 1997

As chip densities increase, conventional methods of testing become more difficult. One way around this problem is to use the extra circuitry made available by including self-test logic on the chip. Typically, the self-test circuitry includes a linear shift register to generate the test input sequence and a second shift register network to compact the outputs of the circuit into a small result, called a signature, that can be compared to the result from a properly functioning circuit. If a single output from the circuit is used, it is called a serial signature. If multiple outputs are used, the result is called a parallel signature. Of course, there is a risk that the compaction process will produce the signature of a properly functioning chip when the chip is actually defective. This problem is known as aliasing. The primary aim of this paper is to provide an upper bound on the probability of an alias error, based on the length of the test sequence, the size of the shift register in the compactor, the number of outputs in the circuit, and the number of signature samples used.

This paper breaks new ground, since previous work has concentrated on alias error probabilities for serial signatures. The authors correct some errors in the existing literature on serial signatures before turning their attention to the primary result on parallel signatures. If good research creates new problems to replace those it solves, then this paper qualifies. The gap between the serial bound and the parallel bound for one input suggests that there is considerable room for improvement in the parallel bound. If not, then someone needs to explain why serial signatures are so much more amenable. Also, the failure analysis focuses strictly on combinational circuits. This means that failures within the self-test circuitry cannot be treated by the methods used here. Whether this limitation limits the applicability of this work in the real world remains to be seen, but extending this research to include the self-test logic would seem to be a promising area for further research. Extending it to sequential circuits looks like a more challenging problem.

The paper can be understood by experts and nonexperts in VLSI design and testing; people outside of this field, however, are less likely to be interested in this cutting-edge research.

Reviewer:  D. M. Bowen Review #: CR121066 (9711-0905)
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Built-In Tests (B.7.3 ... )
 
 
Built-In Tests (B.6.2 ... )
 
 
Combinational Logic (B.6.1 ... )
 
 
Diagnostics (B.2.3 ... )
 
 
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