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Logic synthesis using Synopsys (2nd ed.)
Kurup P., Abbasi T., Kluwer Academic Publishers, Norwell, MA, 1997. Type: Book (9780792397861)
Date Reviewed: Jul 1 1998

The authors state in their preface that “this book is not a VHDL or Verilog primer” and that prior knowledge of  either  language is essential to finding the book useful. They say that the first chapter contains an overview of application-specific integrated circuit (ASIC) design and that a number of useful examples of good design practice follow. Unfortunately, in the absence of a basic manual for either VHDL or Verilog, I cannot comment in any meaningful way, particularly because such references as are provided are not at all helpful (for instance, “1. Design Compiler Reference Manual” and “2. Designware User Guide”).

The kinds of examples examined are typified by D-type flip-flops and latches and various sorts of gate elements, although toward the end of the book, a more extended example is provided in the form of a bubble-sort device.

The book is very hard to read because of the continual use of acronyms. There is no extended bibliography, and, as mentioned, the references offer no help. Thus, the book may be of use to experts in the systems mentioned but would be quite unsuitable as a course text at any level.

Reviewer:  A. D. Booth Review #: CR121219 (9807-0471)
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Types And Design Styles (B.7.1 )
 
 
Automatic Synthesis (B.6.3 ... )
 
 
Hardware Description Languages (B.6.3 ... )
 
 
Optimization (B.6.3 ... )
 
 
VHDL (B.6.3 ... )
 
 
Design Aids (B.7.2 )
 
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