Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
Blelloch G., Gibbons P., Matias Y., Zagha M. IEEE Transactions on Parallel and Distributed Systems8 (9):943-958,1997.Type:Article
Date Reviewed: Jun 1 1998

An analytical model for predicting the performance of algorithms on a shared-memory multiprocessor is presented. The experiments use synthetic programs and four algorithms: for binary search, random permutation, sparse matrix multiplication, and finding connected components of a graph. The model predicts the performance of these programs quite well on the Cray C90 and J90 machines. One of the major limitations of the model, as the authors point out, is the lack of cache effects. This limitation reduces the accuracy and applicability of this model for current and near-future shared-memory machines. For practical purposes, the model should be extended.

This research paper fulfills its basic purpose of including memory contention and delay in the model. Its best features include the authors’ intuitive description of the theorems and clear explanation of the algorithms. The paper is well presented, and people in the area of performance analysis will find it useful.

Reviewer:  Farnaz Toussi Review #: CR121371 (9806-0415)
Bookmark and Share
 
Performance Analysis And Design Aids (B.3.3 )
 
 
Multiple Data Stream Architectures (Multiprocessors) (C.1.2 )
 
 
Performance of Systems (C.4 )
 
Would you recommend this review?
yes
no
Other reviews under "Performance Analysis And Design Aids": Date
Architecting phase change memory as a scalable DRAM alternative
Lee B., Ipek E., Mutlu O., Burger D. ACM SIGARCH Computer Architecture News 37(3): 2-13, 2009. Type: Article
Oct 28 2009
Flash as cache extension for online transactional workloads
Kang W., Lee S., Moon B. The VLDB Journal: The International Journal on Very Large Data Bases 25(5): 673-694, 2016. Type: Article
Dec 20 2016
Dynamic core allocation and packet scheduling in multicore network processors
Iqbal M., Holt J., Ryoo J., de Veciana G., John L. IEEE Transactions on Computers 65(12): 3646-3660, 2016. Type: Article
Mar 31 2017
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud®
Terms of Use
| Privacy Policy