The design of a digital system involves combinatorial circuits, latches, and clock circuits that require a careful timing analysis. Because of the delays introduced by the modules, it is necessary to ensure that the signals arrive at proper times with respect to the clock. The overall system must not fail due to accumulation of effects of skew, pulse widths, and data paths of different lengths. The authors address this issue more generally than in earlier work; they base the development on practical observations.

Part C begins the paper with the basic time definitions related to latches, such as pulse width, setup time, and hold-time. The authors introduce a new parameter called “sample start time” and define two latch mode operations (clock controlled and data controlled). All these concepts are illustrated. Part D defines quantities such as clock “skew” and “skew hierarchy”; skew hierarchy is the new concept contributed by this paper. The authors remove the restrictions placed on the clock phases in previous research.

Part E defines the problem addressed in this paper. The timing rules of the circuits involving latches must be such that if piecemeal parts are designed according to the rules, then the whole system, made of these parts, should function correctly.

Part F is the core of the paper. After a few more definitions, theorem 2 gives the latch-to-latch timing rule. Basically, the rules give two inequalities, MAX and MIN. These give upper and lower bounds on the propagation delay for the combinational logic between two consecutive latches. The rest of this part gives both intuitive and formal proofs of the theorem. Finally, part G discusses the application of the timing rule in practice, including a discussion on automated timing analysis.

The paper is well written and well illustrated. It makes a useful contribution to this important practical aspect of digital system design.