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Testing Schemes for FIR Filter Structures
Mukherjee N., Rajski J., Tyszer J. IEEE Transactions on Computers50 (7):674-688,2001.Type:Article
Date Reviewed: Jul 18 2002

This is a very interesting research paper. The presentation is very formal, and some mathematical background is required to understand the results. It will be of interest to those involved in the theory and practice of testing, as well to those directly involved in the design of FIR chips.

The paper presents a new pseudoexhaustive test methodology guaranteed to detect all combinational faults in the basic cells of all functional blocks in digital finite impulse response (FIR) filters. Separate sections treat FIFO Buffer-Comb filters, constant input multipliers, trees of adders, and phase shift multipliers. Using only simple arithmetic functions, the concept of exhaustive coverage of contiguous input subspaces is applied to develop test vectors that exhaustively cover any specific subspace size at the input to a functional block without the need for functional modeling or expensive fault simulation. Existing registers in the filter structure act as parallel scan chains to enhance the controllability of deeply embedded structures. Other existing pipeline registers are used to hold and apply the test vectors. Therefore, fairly minimal modifications need to be made to the original filter to implement the testing scheme.

This paper is well written and apparently free of technical errors. It is essential reading for those performing research in testing and for those designing FIR chips.

Reviewer:  F. Gail Gray Review #: CR126273 (0209-0505)
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Test Generation (B.2.3 ... )
 
 
Signal Processing Systems (C.3 ... )
 
 
Test Generation (B.6.2 ... )
 
 
Verification (B.6.3 ... )
 
 
Design Aids (B.6.3 )
 
 
Reliability And Testing (B.6.2 )
 
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