The reproduction of MPEG audio files is becoming a hot topic in both the scientific and entertainment arenas, motivating a lot of research in the area with the goal of achieving high performance with contained power consumption. Since the algorithms are already defined, the key point in improving the final product is now to customize the design architecture.

A semi-ASIC architecture is proposed, with an embedded RISC processor, working at a low voltage and low operation speed for decoding MPEG-2 audio streams. This architecture is derived from an analysis of the computation-intensive parts of the MPEG-2 decoding algorithm: dedicated specific hardware is designed for decoding, and a RISC core is used to execute the expensive decision-making procedures.

Because of an uncommon number of English errors, the discussion is sometimes difficult to follow. The paper seems to gather results achieved in the past, introducing new elements to improve the performance of the final design, which achieves the desired performance and power requirements. It is unclear if, or how, the quality of the decoded audio would be affected.