A proposal to combine previous techniques to make better use of resources (registers) in superscalar processors, based on early recycling, is presented in this paper. This new technique was tested on both a load/store queue and reorder buffer.

The major weakness in this approach is that the point of no return is hard to detect. In addition to this shortcoming, the authors do not consider hardware volume or data dependences among instructions, and do not present the implications for Tomasulo’s algorithm or details about the target pipeline. They also fail to compare their technique’s performance to related techniques, as opposed to the baseline architecture.

The paper is satisfactorily written and organized. The basic idea seems be interesting, but not very new, and some points in the text are unclear.