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Design and analysis of low-power cache using two-level filter scheme
Chang Y., Ruan S., Lai F. IEEE Transactions on Very Large Scale Integration (VLSI) Systems11 (4):568-580,2003.Type:Article
Date Reviewed: Jan 21 2004

It is well known that modern computers increase their computational power at a rate larger than Moore’s law. What it is not common knowledge is that the electrical power consumption of modern processors is increasing as well.

Many efforts have been made to reduce power consumption in modern processors, but these address the classical parts of computer architecture, such as the control unit or arithmetic-logic unit (ALU). In an environment in which first- and second-level cache memories are moving onto the chip, however, cache memories are now the best candidate for obtaining further reductions. Twenty-five percent of the total chip power consumption for the Digital Equipment Corporation’s 21164s, and 43 percent of power consumption for Intel’s StrongArm (SA) 110 processor is devoted to cache operations.

This paper proposes a new architectural solution to drastically reduce power consumption. The solution is based on a two-level filter that is used to avoid useless accesses to the cache. The first level of filtration is based on well-known block buffer techniques, in which, exploiting the spatial locality of memory references, two or more consecutive references are loaded to prefetch data. The second level, in contrast, is based on a sentry-tag; that is, the use of a certain number of tag bits to check the correctness of the access way. The rationale behind this strategy is that this will prevent useless comparisons of tags for those ways that do not have this minimum requirement.

These modifications are obtained at little hardware overhead cost, and have the unique characteristic of being independent of software and industry standard architecture.

To evaluate the performance of this strategy, an analytical model is used to enumerate saved operations, and thus reduced power consumption. Experimental evidence of a reduction is provided for different parameters of the two filters. Analysis is performed via simulation, both at the resistor-transistor logic (RTL) level, and at the implementation level. Overall cache consumption reduction with the two-level filter is more than 50 percent, for both I-cache and D-cache.

Reviewer:  Andrea Prati Review #: CR128963 (0406-0663)
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Miscellaneous (B.3.m )
 
 
Cache Memories (B.3.2 ... )
 
 
VLSI Systems (C.5.4 )
 
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