Ciriani, Luccio, and Pagli apply earlier work on sum of pseudoproducts (SPP) expressions of Boolean functions to the synthesis of integer multiplication circuits. A pseudoproduct is a generalization of the AND-products of Boolean variables, where any of the variables may be replaced by the XOR of any number of variables. Earlier work showed that, in many cases, the use of SPP expressions instead of sum of products (SOP) expressions results in a strong reduction in the number of implicants/pseudoproducts and literals. This work investigates the results of SPP synthesis for two standard multiplier structures, culminating in a comparison of their very large scale integration (VLSI) implementations with those of standard SOP circuits, on the basis of power consumption, circuit speed, and chip area.
The final results in the paper show SPP yielding dramatic improvements in total area and maximum delay for 16 x 16 and 54 x 54 multipliers, with area dropping to 83 percent, and delay dropping to 84 percent in the former case, and area dropping to 71 percent, and delay dropping to 69 percent in the latter.
Unfortunately, earlier data presented for modules (carry-save full adder blocks, with varying numbers of input bits, and non-additive 4 x 4 multiply modules) does not justify the authors’ claim that “for the vast majority of modules in Tables 5 and 6 [an apparent misprint; it should probably say Tables 4 and 5], the SPP forms require less area, delay, and power than the corresponding SOP forms, for each of the libraries used.” Inspection of the tabular data shows that, in fact, only three of eight modules (AD5, AD9, and MM) have this property. Perhaps the data was published incorrectly.
