This work introduces a new cache (static random access memory (SRAM)) memory cell, composed of asymmetric transistors, and intended to reduce leakage current, and, consequently, power dissipation.

The design of this cell is based on the assumption that the memory value streams of ordinary programs are biased toward zero. Working on this assumption, the authors provide the asymmetric cell with a set of transistors with high voltage, instead of leaking transistors, when the cell is in zero state. The authors introduce three scenarios possible in the zero state: first, that there is no performance degradation, no stability loss, and a power leakage reduction by a factor of two; second, that there is no performance degradation, a six percent stability loss, and a power leakage reduction by a factor of seven; and third, that there is a one percent performance degradation, no stability loss, a power leakage reduction by a factor of 58, and a 25 percent area increase.

My main concern is how well the authors’ assumption--that memory values for programs are biased toward zero--stands up in ordinary programs. In the case of instructions, one could design an instruction set architecture to possess this property (having more zeros). To investigate such a claim for the data portion of memory, the authors should have performed an empirical experiment. Although the authors of this paper refer to Hennessy and Patterson’s book on architecture [1] to support their claim, I am not convinced by even those authors’ arguments. I would prefer to see results for some set of benchmarks, for example for a subset of the SPECint 2000 benchmark suite. Overall, this is a valuable work, especially in the design of digital signal processing (DSP) applications, and of multimedia processors where power is an issue.