The data-cache performance of various discrete wavelet transform (DWT) production approaches on instruction-set platforms is analyzed in this paper. The authors do not address the arithmetic or instruction-related complexity of these applications.

In the first part, the authors propose single-processor software designs for all the transform-production methods. Based on this approach, analytical equations are proposed that allow for the prediction of the expected number of data-cache misses in a generic memory hierarchy. The validity of the proposed equations is bounded by a set of constraints for the cache characteristics.

Although theoretical analysis does not seek to predict precisely the number of misses in a specified cache architecture, in order to verify the theoretical framework and compare the proposed software designs, results are presented from simulations, and from implementation on a real platform. It is shown that data-related cache penalties are expected to dominate the execution of the two-dimensional multilevel DWT in typical programmable platforms, since they are more frequent by far than the instruction-related cache penalties.

The paper also presents a theoretical framework for the analytical estimation of the data-related misses, which can be used for high-level parametrical estimation of DWT implementation efficiency in a variety of cache architectures.