The best book ever published on the topic of verification was the first edition of this book [1]. Having used the first edition extensively, I must say how amazing it is that Bergeron, in his masterpiece second edition, did an even better job.

There are quite a few books on verification and the principles of verifiable design. Almost every serious Verilog/very high-speed integrated circuit hardware description language (VHDL) book also includes a chapter on writing testbenches. Many wonderful tutorials on the topic exist from companies like Aldec, for example. This book, however, is unique in its style and approach. The style is friendly and precise at the same time; the approach is one of thorough analysis and attention to detail. The book is a must for every application-specific integrated circuit (ASIC)/field-programmable gate array (FPGA) design engineer, and is well worth of every penny spent for it.

Bergeron teaches readers the principles of verification, the tools (such as lint, simulators, and code coverage), the planning process for verification, and high level modeling and simulation management, and includes a “must memorize” appendix on coding style. Many companies have included in their internal coding style guidelines excerpts from the first edition of this book, or recommendations based on it.

This book also presents a proven and reliable methodology, which any engineer could use in good faith in his or her work. In short, if the reader of this short review is involved in ASIC/FPGA design, the first book to get, after a good Verilog/VHDL reference, is this one (which, of course, is not limited to Verilog/VHDL).