An elementary introduction to reduced instruction set computing (RISC) processors, with an overall emphasis on the machine-level language and not on functional chip design, is presented in this book. It is split into three sections: a brief comparison of complex instruction set computing (CISC) and RISC designs, an overview of a number of current RISC chips, and a large section on assembly-level programming based on the microprocessor without interlocked pipeline stages (MIPS) RISC architecture. The book does not concern itself with advanced aspects of processor design, and only briefly mentions branch prediction. There is no discussion of cache or memory page access, and there is only a brief mention of pipelining and multiprocessing units.
The first section describes the concepts of an instruction set architecture (ISA), comparing the CISC with the RISC approach. The concepts of ISA instruction types and formats, addressing modes, and load/store architecture are introduced. The discussion continues with descriptions of flow control, unconditional and conditional branching, and branch prediction methods. The section then introduces procedure calls and parameter passing techniques, and concludes with an overview of RISC ISA principles.
The second section describes features and functions of a number of RISC processors. These include MIPS, scalable processor architecture (SPARC), PowerPC, Itanium, and ARM. The MIPS is only briefly discussed here. For the other processors, each chapter begins with a discussion of the registers, addressing modes, instruction set, and instruction format. Each chapter then describes typical instructions for arithmetic, logical, and branch operations. In the case of the Itanium processor, there are descriptions of instruction parallelism with bundles and Itanium branch prediction and elimination.
The final section, which encompasses over half of the book, incorporates an introduction to assembly-level programming based on the MIPS architecture. All of the examples are based on using a MIPS 2000 simulator called SPIM, which is freely available on the Internet and incorporates an assembler, runtime simulator with simple system calls, and a debugger. SPIM simulates the older MIPS 2000, and does not handle delayed branches. This section has chapters on procedures, addressing modes, arithmetic operations, conditional execution, logical and shift operations, recursion, and floating point operations. Each chapter describes the appropriate instruction sets, condition codes, and sample instructions, and illustrates each type with several simple examples. Illustrations include parameter passing in registers, stack operations, array handling, leaf and nonleaf procedures, and recursion. Examples include simple sums, calculating Fibonacci numbers with both nonrecursion and recursion, digit manipulation (both digit sums and converting integers to strings and visa versa), character manipulation, selection sort, quick sort, and adding floating point numbers.
Even though the MIPS processors are described as being mainly used in embedded applications, all of the examples are simple mathematical examples. No examples are given of how embedded systems work, and, although exceptions are mentioned, no information is provided about how they are handled. There is also no information about interrupts and interrupt handling, topics that are essential for embedded systems. This book is similar to a number of other books on RISC assembler programming [1,2,3]. On the other hand, it is not as comprehensive as some other books on the topic [4,5,6].