This paper proposes a mechanism, eager misprediction recovery (EMR), for recovering the processor state after branch misprediction in modern out-of-order architectures. The idea of this mechanism is to restart the instruction fetching on the correct path without having to restore the renaming table, thereby naturally repairing it during the execution on the correct path. Thus, after a branch misprediction, the useful instructions continue to be executed with no interruption, in parallel to restarted fetching, and the speculative instructions wait for the repaired values in the renaming table.

This paper outlines the necessary changes for identifying, handling, and repairing the speculative state in the pipeline. EMR experiments were done on 17 SPEC 2000 benchmarks, showing significant results. The idea is very interesting and important. However, the main concern is the complexity of a real implementation. Restoring the renaming table entirely is easier than handling its entries individually. The necessary logic to implement the EMR can have an impact on the cycle time. The authors do not discuss this tradeoff. Except for this question, it is a very good work.