This is a relevant piece of work in the domain of dynamic code compression and decompression in deeply embedded central processing units. The authors identify the code between two branch/jump targets as a potentially good candidate for compression in embedded very long instruction word (VLIW) architectures, and discuss a novel, adaptive, Lempel-Ziv-Welch (LZW)-based compression scheme capable of compressing such irregular memory blocks.

A good overview of other research in the domain of dynamic code compression/decompression is provided, and the authors make the observation that most schemes rely on fixed-size memory blocks as input to the compression/decompression hardware. However, the authors have lifted this deficiency by developing a proprietary engine that works with variable-size memory blocks as inputs. As these variable-size blocks are typically larger than the fixed-size blocks used in the literature, they allow for relative freedom in the choice of the compression/decompression algorithms.

The authors make a distinction between the pre-cache and post-cache decompression engine configurations, and choose the latter, as it provides the best input bandwidth to the decompression engine. This is a valid point, as use of the pre-cache architecture would have mandated the use of the narrower on-chip bus, and the on-chip bus would have reduced the output bandwidth of the decompression engine. In addition, the authors use an established technique (local area transport) to correlate the compressed address space to the noncompressed memory space.

Lin et al. chose to use LZW compression/decompression, and studied two ways to keep track of branch/jump targets. First is the use of an additional list, which relies on a full associative comparison of the compressed PC to the branch/jump target addresses in the compressed address space. This is a well-known technique that suffers from large power consumption, as typical register transfer level (RTL)-based implementations of such a structure rely on the use of flops. Second is the use of an exception index to point to those branch/jump target addresses in the compressed address space. This is the chosen method in this work.

The authors further discuss their engine, which is based on an adaptive, modified LZW implementation. It allows for the application of different compression algorithms, based on the size of the branch blocks. Results indicate that the two schemes implemented, with and without dynamic LZW, are better than the other schemes reported in the literature, peaking at a decompression bandwidth of 1.82 bytes per cycle. Finally, results from both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations are presented, demonstrating that the proposed methodology is indeed viable.

Overall, the paper is particularly interesting and relevant to the computer architecture research community, as it address the well-known problem of reduced instruction set computer (and more importantly, VLIW) code density. The solution discussed is indeed novel and valid, and demonstrates a very good understanding of these issues. A minor point of criticism would be the lack of detail in using the proposed scheme for the case of a VLIW processor, which is understandable as this is a four-page conference paper.