This book offers a very easy way to grasp the basics of both computer architecture and Verilog. It shows the reader, step-by-step, how to use a hardware description language (HDL) as a tool for developing a simple processor.

In chapter 2, the book concisely exposes the reader to Verilog. A reader with no background in HDLs will find this introduction incomprehensible. However, as the reader proceeds to the remaining chapters, several HDL concepts will become clear.

Chapter 3 introduces the reader to the basic steps needed to describe a complete instruction set architecture (ISA), using a simple processor example called VeSPA (very small processor architecture). These basic concepts are presented in a simple-to-follow way. In chapter 4, the authors present a behavioral description model for implementing VeSPA’s machine language, while chapter 5 describes the design of a two-pass assembler to convert programs written in VeSPA assembly language into machine code. The concept of pipelining for speeding up the processor is introduced in chapter 6, with a brief description of how to detect pipeline hazards.

The behavioral model described in chapter 4 and the pipeline processor introduced in chapter 6 are developed in chapter 7. In this chapter, a detailed structural description of a five-stage pipelined version of VeSPA is presented. Several design tradeoffs made at each stage of the pipeline process are discussed. However, the Verilog implementation of the pipeline processor is not described (its code is available on the book’s companion Web site). The book concludes with a chapter that presents various testing techniques for verifying the operation of the entire VeSPA processor.

Overall, the materials presented in the book are well organized and easy to follow. In each chapter, the authors introduce the design problem, present a basic solution, and then tune the solution until it meets all of the design specifications. The book proposes a list of references at the end of each chapter for readers who seek more detailed information on the topics presented.

The book does have some drawbacks; there are very few examples or diagrams to illustrate the various concepts presented, and to generate interest in the book. This will cause difficulty for beginners who are trying to gain a full understanding of the important techniques presented.

The book can be regarded as a very precise, clear, simple, and intuitive guide to the use of Verilog in designing and modeling a complete digital system. This well-organized book can be used as an excellent supplement to a computer architecture course at the senior undergraduate or beginning graduate level, where an HDL is required to specify, design, and test a complete processor.