The Liberty simulation infrastructure models chip area, wire length, and power consumption. This paper presents an interesting modeling system, Justice, that is a set of extensions to Liberty.

The authors begin their presentation with an overview of the Liberty simulation environment, followed by a description of Justice and their power, area, and wire models. Based on an architectural specification of a processor, this system estimates the area and per-access power consumption of each module in the architecture, constructs a floor plan for the processor, and then computes the length and delay of critical communication paths. Finally, the system modifies the architectural specification, and generates an executable simulator for the processor.

The authors evaluate the system’s capabilities by simulating a number of very long instruction word (VLIW) processors, illustrating the tradeoffs among area, power consumption, and performance in these architectures. While these simulations are somewhat idealized, they seem to be sufficient to illustrate the importance of modeling technology effects when evaluating potential changes to a computer architecture. The authors end with a discussion of related work.

The results provided enable designers to compare the costs and benefits of different changes to an architecture, and demonstrate the importance of considering wire delay early in the design process. The authors believe that simulation tools such as their system enable designers to easily model technology effects in their simulations; such tools will become indispensable for computer architects. In general, this is a well-written paper, intended for professionals.