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ADOFs and resistive-ADOFs in SRAM address decoders: test conditions and March solutions
Dilillo L., Girard P., Pravossoudovitch S., Virazel A., Borri S., Hage-Hassan M. Journal of Electronic Testing: Theory and Applications22 (3):287-296,2006.Type:Article
Date Reviewed: Dec 13 2006

The title of this paper says it all. The paper examines address decoder open faults (ADOFs) and resistive-ADOFs (not quite open, but where an unexpected resistance is present). Circuit simulations determine conditions that are sufficient for detecting both types of faults; it was not stated whether a commercial simulator or an in-house simulator was used. Existing March tests can be used to detect the faults if the addressing sequence is modified so that every pair of addresses that differ by only one binary bit occurs sequentially somewhere in the sequence of addresses applied during the test.

The same results are reported by Otterstedt et al. [1]. Although the authors give this paper some credit, they never explicitly state that the paper contains the same sufficient test conditions reported in their own paper. Both papers show that the complexity of the March tests and the ability of the March test to detect other faults that are address sequence invariant are unaffected. This paper did not contain an analysis of the increased complexity of the address generator, which would affect the hardware complexity in a built-in self test (BIST) implementation, or the execution time of the address-generating algorithm in a microprocessor-controlled testing procedure (Otterstedt’s paper did contain such an analysis).

Although this paper is not as original as it might seem at first glance, there is original material here. The primary contribution seems to be the introduction and analysis of resistive-ADOFs. It would be interesting to know what the probability of such faults might be in current technologies.

Reviewer:  F. Gail Gray Review #: CR133700 (0711-1107)
1) Otterstedt, J.; Niggemeyer, D.; Williams, T.W. Detection of CMOS address decoder open faults with March and pseudorandom memory tests. In Proc. of the International Test Conference IEEE, 1998, 53–62.
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Static Memory (SRAM) (B.3.1 ... )
 
 
Cache Memories (B.3.2 ... )
 
 
Design Styles (B.3.2 )
 
 
Reliability, Testing, And Fault-Tolerance (B.8.1 )
 
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