Homayoun et al. contend that increasing the size of processor resources is not an effective way to improve performance, due to constraints on achievable clock frequency during operation. In fact, while increasing the size of processor resources, such as the reorder buffer, instruction queue, and register file, can deliver a higher number of instructions per cycle, the effect the resource increase has on achievable operating frequency can have a negative impact, resulting in an overall degradation of execution time. They observe that after either one L2 cache miss or several L1 cache misses, one of the incremented resources completely fills, becoming a performance bottleneck.

They propose two adaptive resource resizing techniques, namely L2RS and L2ML1RS, by exploiting cache misses. The results of experiments run across SPEC2K benchmarking show significant improvements in performance and energy-delay reduction on both approximations. The proposed solution adapts the resource size by upsizing only during cache misses; that is, during normal periods, resources are kept at their normal level, and during a cache miss period, resources are incremented. Pipelining on these upsized resources permits meeting frequency targets.

One of the most interesting features of the proposal is that the authors also present the circuit modification to realize the approximations, which seems very simple.